Robust Boolean reasoning for equivalence checking and functional property verification

Kuehlmann, Andreas; Paruthi, Viresh; Krohm, F.; Ganai, Malay K.

doi:10.1109/tcad.2002.804386

Cited by 247 publications

(179 citation statements)

References 21 publications

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“…All experiments were run on an IBM pSeries computer with POWER4 processors running at 1.4GHz using the IBM internal verification tool SixthSense. All designs were put through reductions using a BDD-based combinational redundancy removal engine [16] before the symbolic simulator was applied. FPU ADD and FPU FMA are the verification problems of the dataflow for a floating-point "add" and "fused-multiplyadd" instruction respectively [13].…”

Section: Experimental Results and Conclusionmentioning

confidence: 99%

“…We map all designs into a netlist representation containing only primary inputs, one "constant zero" node, 2-input AND gates, inverters, and registers, using straightforward logic synthesis techniques to eliminate more complex gate types [16]. Inverters are represented implicitly as edge attributes in the representation.…”

Section: Netlists: Syntax and Semanticsmentioning

confidence: 99%

“…For example, redundancy removal and logic rewriting algorithms [16] that reduce the number of gates in the netlist reduce the number of distinct BDDs that need to be built, and may even reduce the cutwidth of the netlist implying a need for fewer live BDD nodes. In a CBSS approach, reductions to the sequential netlist are particularly useful, as they reduce the complexity of every subsequent time-frame of the symbolic evaluation.…”

Section: Transformation Synergiesmentioning

confidence: 99%

“…The engine thus uncovers large portions of the state space, and allows for probabilistically uncommon scenarios to be exposed that cause the fail events to be hit. When performing an exhaustive k-step bounded model check of the design, the symbolic simulator often outperforms SAT-based bounded model checking [16], particularly when the number of inputs is not too large or for small values of k. Additionally, we have found this engine to be very useful when attempting proofs via k-step BDDbased induction. Furthermore, the engine may be used to obtain proofs in conjunction with an engine that computes a diameter estimate of the design [3].…”

Section: Transformation Synergiesmentioning

confidence: 99%

“…Even modern satisfiability solvers, increasingly finding applications in domains for which BDD-based techniques were long considered the only alternative (such as unbounded verification), are likely to use a hybridalgorithm scheme integrating BDDs for optimality [16,15].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

Paruthi¹,

Jacobi

Weber

2005

Lecture Notes in Computer Science

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Abstract. Most computer-aided design frameworks rely upon building BDD representations from netlist descriptions. In this paper, we present efficient algorithms for building BDDs from netlists. First, we introduce a dynamic scheduling algorithm for building BDDs for gates of the netlist, using an efficient hybrid of depth-and breadth-first traversal, and constant propagation. Second, we introduce a dynamic algorithm for optimally leveraging constraints and invariants as don'tcares during the building of BDDs for intermediate gates. Third, we present an automated and complete case splitting approach which is triggered by resource bounds. Unlike prior work in case splitting which focused upon variable cofactoring, our approach leverages the full power of our don't-caring solution and intelligently selects arbitrary functions to apply as constraints to maximally reduce peak BDD size while minimizing the number of cases to be explored. While these techniques may be applied to enhance the building of BDDs for arbitrary applications, we focus on their application within cycle-based symbolic simulation. Experiments confirm the effectiveness of these synergistic approaches in enabling optimal BDD building with minimal resources.

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Section: Experimental Results and Conclusionmentioning

confidence: 99%

Section: Netlists: Syntax and Semanticsmentioning

confidence: 99%

Section: Transformation Synergiesmentioning

confidence: 99%

Section: Transformation Synergiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

Paruthi¹,

Jacobi

Weber

2005

Lecture Notes in Computer Science

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Effective Preprocessing in SAT Through Variable and Clause Elimination

Eén

Biere

2005

Lecture Notes in Computer Science

424

388

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Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies

Baumgartner¹,

Mony²

2005

Lecture Notes in Computer Science

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Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present several fully-automated techniques to enable maximal input reductions of sequential netlists. First, we present a novel min-cut based localization refinement scheme for yielding a safely overapproximated netlist with minimal input count. Second, we present a novel form of reparameterization: as a trace-equivalence preserving structural abstraction, which provably renders a netlist with input count at most a constant factor of register count. In contrast to prior research in reparameterization to offset input growth during symbolic simulation, we are the first to explore this technique as a structural transformation for sequential netlists, enabling its benefits to general verification flows. In particular, we detail the synergy between these input-reducing abstractions, and with other transformations such as retiming which-as with traditional localization approaches-risks substantially increasing input count as a byproduct of its register reductions. Experiments confirm that the complementary reduction strategy enabled by our techniques is necessary for iteratively reducing large problems while keeping both proof-fatal design size metrics-register count and input countwithin reasonable limits, ultimately enabling an efficient automated solution.

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Robust Boolean reasoning for equivalence checking and functional property verification

Cited by 247 publications

References 21 publications

Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

Effective Preprocessing in SAT Through Variable and Clause Elimination

Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies

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