Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

Cho, Seong-Jae; O’uchi, S.; Endo, Kazuhiko; Kim, Sang Wan; Son, Younghwan; Kang, In Man; Masahara, Meishoku; Harris, James S.; Park, Byung‐Gook

doi:10.5573/jsts.2010.10.4.265

Cited by 5 publications

(2 citation statements)

References 27 publications

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“…The common approach to FinFET implantation is the socalled double-sided implantation, that is to implant half the desired dose from one side of the fin and the other half from the other side [7], [12], [13]. A schematic of double-sided implantations by tilted beam for the fin is shown in Fig.…”

Section: Analytical Modelsmentioning

confidence: 99%

“…Alternatives to ion implantation techniques such as plasma immersion doping [9]- [11], which theoretically could deliver more conformal doping, still need extensive investigation and development. Meanwhile, ion implantation remains a major method for fin doping [7], [12], [13]. Traditionally, the commonly used methods in technology computeraided design tools for the simulation of ion implantations include Monte Carlo method [14]- [18] and the distribution moments method [16], [19]- [21].…”

Section: Introductionmentioning

confidence: 99%

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Analytical Models for Three-Dimensional Ion Implantation Profiles in FinFETs

Wang

Brown

Cheng

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A set of analytical models based on the Pearson distribution function applied to the modeling of ion implantations in the 3-D structure of FinFETs is presented. The method provides a succinct way to simulate the doping profiles in FinFETs at low computational cost. Compared to previous analytical methods based on Gaussian distributions, this approach handles more realistic asymmetrical doping distributions arising from ion implantation. A simulation module in C + + has been developed to model ion implantations in FinFETs based on this analytical approach. The simulation module is demonstrated in an example simulation of a silicon-on-insulator FinFET with physical gate length of 20 nm.

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Section: Analytical Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analytical Models for Three-Dimensional Ion Implantation Profiles in FinFETs

Wang

Brown

Cheng

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

Navlakha

Kranti

2017

Journal of Applied Physics

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Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

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