2010
DOI: 10.1002/adma.201001865
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Revealing Buried Interfaces to Understand the Origins of Threshold Voltage Shifts in Organic Field‐Effect Transistors

Abstract: The semiconductor of an organic field‐effect transistor is stripped with adhesive tape, yielding an exposed gate dielectric, accessible for various characterization techniques. By using scanning Kelvin probe microscopy we reveal that trapped charges after gate bias stress are located at the gate dielectric and not in the semiconductor. Charging of the gate dielectric is confirmed by the fact that the threshold voltage shift remains, when a pristine organic semiconductor is deposited on the exposed gate dielect… Show more

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Cited by 106 publications
(99 citation statements)
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“…bias stress effects). [17] These shortcomings, combined with the limiting air-instability typically observed for organic semiconductors, make still unclear whether solution deposition will offer sufficient technological and commercial advantages over the existing inorganic technologies.…”
Section: Introductionmentioning
confidence: 99%
“…bias stress effects). [17] These shortcomings, combined with the limiting air-instability typically observed for organic semiconductors, make still unclear whether solution deposition will offer sufficient technological and commercial advantages over the existing inorganic technologies.…”
Section: Introductionmentioning
confidence: 99%
“…17 Mathijssen et al repported bias stress in OFETs-prepared on heavily doped Si wafers acting as a common gate with 200 nm thermally grown SiO 2 gate dielectric-to be caused by charge trapping in the gate dielectric established by the fact that the threshold voltage shift is sustained upon depositing a pristine organic semiconductor on the exposed dielectric of a stressed and delaminated transistor. 18 Wang et al correlate bias stress instability in pentacene thin film transistors (TFTs) to the timedependent charge trapping in both the channel and the metal/ organic contact regions since they found that the shift in threshold voltage is accompanied by an increase in contact resistance. 19 Street et al suggested that formation of hole bipolarons is responsible for the observed bias stress effect in polymer TFTs, given that the number of holes removed from the channel per time and area is proportional to the square of their concentration.…”
mentioning
confidence: 99%
“…The revealed gate dielectric is then accessible for characterization with scanning Kelvin probe microscopy (SKPM). 9,10 This technique was earlier applied to reveal the location of trapped charges due to gate bias stress 11 and to link the threshold voltage shift in a transistor with a SAM-modified gate dielectric to charges trapped by the SAM. 12 To apply the exfoliation technique, we choose organic semiconductors.…”
mentioning
confidence: 99%