Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA

Kundi, Dur-e-Shahwar; Aziz, Arshad; Ikram, Nassar

doi:10.1016/j.ipl.2010.03.004

Cited by 10 publications

(5 citation statements)

References 10 publications

(10 reference statements)

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“…Several Look‐Up‐Table‐based AES implementations are proposed using the dedicated embedded memories of FPGA, that is, BRAM instead of using the FPGA logic resources. The size of BRAM in modern Xilinx FPGAs such as Atrix‐7 and Virtex‐5 is 32 Kb ].…”

Section: Related Workmentioning

confidence: 99%

“…But to further reduce the BRAM resources for the compact design, we can use two BRAMs iteratively four times in dual mode configuration at the expense of extra clock cycles , or we can access synchronous BRAM multiple times in a single clock cycle by using the multirated clocking technique . The former technique will impose greater latency in the design, while the later will proportionally reduce down the overall system maximum operating frequency.…”

Section: Related Workmentioning

confidence: 99%

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An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

Kundi

Aziz

Kazmi

2014

Security Comm Networks

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In this paper, we present an area efficient Block RAM (BRAM)‐based single unit design of T‐box/T−1‐box on a Field Programmable Gate Array (FPGA) for combined Advanced Encryption Standard (AES) encryption and decryption. Conventional FPGA designs for T‐box module not only utilize several BRAMs for 16 bytes parallel look‐up operations but also because of asymmetric nature of AES, use separate hardware for T−1‐box unit in decryption process. Alternatively in iterative architecture, BRAM in dual‐port mode configuration takes eight clock cycles to access 16 look‐up operations from a T‐box because of its synchronous nature. Thus, resulting in an unoptimized solution not only in term of FPGA resources but also results in high latency for iterative architecture. Our proposed design uses single symmetric T‐box/T−1‐box table with same set of single resource‐shared hardware for both the encryptor and decryptor and at the same time performs eight look‐up operations from single BRAM in one clock cycle using efficient BRAM switching technique instead of using multirated clocking. Our complete 128‐bit symmetric T‐box/T−1‐box design fits into just 2 BRAMs and 136 Slices. It occupies lowest area reported to date with 50% power saving and highest Throughput Per Slice (TPS) of 10.77. Copyright © 2014 John Wiley & Sons, Ltd.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

Kundi

Aziz

Kazmi

2014

Security Comm Networks

Self Cite

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“…Modern generations of FPGA apart from LUTs are now equipped with special embedded features such as multimode clock manager (MMCM) and BRAM for the implementation of high-density and high performance designs. An active area of research in optimization of crypto-system on FPGAs focuses not only to use these new embedded features of FPGA but how efficiently and effectively these features are to be used in order to enhance the performance of these crypto-system in terms of both area and speed [11,12]. Encryption and decryption cores are separately implemented and occupied considerable amount of BRAM resources on FPGA [13].…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Hybrid Model Encryption Algorithm for Secure Transmission of Medical Images

Cha¹,

Sasilatha²

2019

IJEAT

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The advancement of medical field needs a more secure function for sharing the medical related images in the present environment. For making secure transmission of medical images the best solution is cryptography algorithm. There are many cryptography algorithm existing in the market out of the entire algorithm we are select the best encryption algorithm which is really suitable for medical images transmission. Transmission of data is easy at the same time secure transmission are meet the different challenges. To full fill the all the challenges we concentrating the encryption algorithm which is highly secure. For making more secure transmission hybrid model encryption algorithm support more compare to single encryption algorithm. Its having capable of providing confidentiality, authenticity and integrity services to medical images exchanged in telemedicine applications. The same hybrid model encryption may implement in real time application using FPGA device. While implementing in hardware the following factors need to be concentrate more such as power, area, throughput, PSNR, Sensitivity etc. keeping all the factors in mind the hybrid model encryption algorithm are developed for secure transmission of medical images. The aim of the research is to encrypt and decrypt medical images efficiently and effectively protect the transmitted data. This research paper presents a model for encrypting transmitted medical image data. This model uses the following encryption algorithm such as Advanced Encryption Standard, Rivest Cipher 4.

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“…Show day times of FPGA pulled again from LUTs are starting at now furnished with astonishing showed highlights, for example, multi‐mode clock supervisor (MMCM) and BRAM for the execution of high‐thickness and overpowering plans. A dynamic zone of research being made of crypto‐structure on FPGAs centers not exclusively to utilize these new demonstrated highlights of FPGA yet how cutoff and enough these highlights are to be utilized as a touch monster to restore the execution of these crypto‐framework to the degree both range and speed 11,12 . Encryption and disinfecting up centers are savvy finished and had clearing measure of BRAM assets on FPGA 13 .…”

Section: Introductionmentioning

confidence: 99%

Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

Maniam

Sasilatha

2019

Concurrency and Computation

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Summary With the growth of wireless environments, confidential communication has become an important part of daily life. Generally, a wireless medium uses cryptography techniques when transmitting data to provide end‐to‐end protection. Most of the hardware‐efficient cryptosystems do not satisfy the security requirements. In this paper, we concentrate both on security issues and hardware efficiency and present an area‐efficient, high‐throughput hardware structure to implement a hybrid cryptosystem to avoid security problems. The security enhancements are done using a key enhancement process, and it is achieved by using a hybrid encryption cryptosystem. In this paper, we combine block and stream cipher encryption algorithms to frame the hybrid algorithm. We consider advanced encryption standard (AES) as the block cipher and Rivest cipher‐4 (RC4) as the stream cipher. Due to the hybrid systems, performance metrics, such as area, throughput, and power consumptions, are affected. Moreover, advanced arithmetic logic (ie, field arithmetic) combined with the on‐the‐fly key expansion technique is used to minimize area consumption, and parallel subpipeline technique is used to enhance the system throughput. The proposed hybrid architecture (AES‐RC4) is implemented in a field‐programmable gate array with a Xilinx tool.

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Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA

Cited by 10 publications

References 10 publications

An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

Hardware Implementation of Hybrid Model Encryption Algorithm for Secure Transmission of Medical Images

Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

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Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA

Cited by 10 publications

References 10 publications

An efficient single unit T‐box/T−1‐box implementation for 128‐bit AES on FPGA

An efficient single unit T‐box/T−1‐box implementation for 128‐bit AES on FPGA

Hardware Implementation of Hybrid Model Encryption Algorithm for Secure Transmission of Medical Images

Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

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An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA