ReRAM-Based In-Memory Computing for Search Engine and Neural Network Applications

Halawani, Yasmin; Mohammad, Baker; Lebdeh, Muath Abu; Al‐Qutayri, Mahmoud; Al-Sarawi, Said F.

doi:10.1109/jetcas.2019.2909317

Cited by 39 publications

(28 citation statements)

References 47 publications

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“…2. Other advantages of the design include reduced search time and energy [25]. All N filters are flattened into a 1D array and connected together horizontally such that the input will propagate through them at once.…”

Section: A Background On Cnnmentioning

confidence: 99%

“…By utilizing the memristor crossbar architecture, the comparison and the addition of high outputs can be done in a single step. In [25], a memritor-based VR-XNOR cell is presented as shown in Fig. 3.…”

Section: B Memristor-based Xnor Cellmentioning

confidence: 99%

“…Hence, in this paper, we propose an FPGA-based memristor emulator circuit for BCNN. It is an extension of the work presented in [25]. The main contribution of this paper is the implementation and evaluation of the convolution and the pooling modules of a BCNN for handwritten digit recognition problem.…”

Section: Introductionmentioning

confidence: 95%

“…. A match can occur if a black input pixel (presented as 0 V) is compared against a stored black pixel (presented as R OF F ) or if a white input pixel (presented as 1 V) is compared against a stored white pixel (presented (a) Memristor-based binary convolution based on XNOR cell and the similarity output result is stored in the output memritor[25]. (b) A multi-bit XNOR is used to build an array of convolution filters where each filter is represented by a column as presented in .…”

mentioning

confidence: 99%

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FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

et al. 2020

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Binary convolutional neural networks (BCNN) have been proposed in the literature for resource-constrained IoTs nodes and mobile computing devices. Such computing platforms have strict constraints on the power budget, system performance, processing and memory capabilities. Nonetheless, the platforms are still required to efficiently perform classification and matching tasks needed in various applications. The memristor device has shown promising results when utilized for in-memory computing architectures, due to its ability to perform storage and computation using the same physical element. This is in addition to their nonlinear dynamic characteristics that can be used for various applications. Emulating the memristor operation through FPGAs implementation provides flexibility for rapid prototyping and exploration of the design space. In this paper, a FPGA-based memristor emulator circuit is implemented using a multi-bit XNOR gate as the main block for binary convolution which is followed by a memristorbased pooling layer. The BCNN layer is realized by bitwise XNOR-cell followed by wide NOR gate. The implementation has been successfully synthesized and verified using Xilinx Nexys4 FPGA with less than 1% utilization and 144.9 MHz frequency of operation. In order to test the functionality of the proposed cores, a digital implementation for the circuit was realized and verified experimentally. The experimental results show similar performance when compared to software simulation.

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Section: A Background On Cnnmentioning

confidence: 99%

Section: B Memristor-based Xnor Cellmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 95%

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confidence: 99%

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FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

et al. 2020

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“…Content addressable memory (CAM) is an attractive hardware solution for applications that significantly rely on high-speed search, match, and retrieve operations [1][2][3][4] . Unlike conventional SRAM, that takes several cycles for a search operation, a CAM directly performs the search within its pre-stored content in a parallel fashion with potential single cycle access, naturally realizing in-memory computing (IMC).…”

Section: Introductionmentioning

confidence: 99%

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Halawani

Kilani

Hassan

et al. 2021

Preprint

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Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

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Stopping Voltage‐Dependent PCM and RRAM‐Based Neuromorphic Characteristics of Germanium Telluride

Abbas

Ansari

Taha

et al. 2023

Adv Funct Materials

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Recently, phase change chalcogenides, such as monochalcogenides, are reported as switching materials for conduction‐bridge‐based memristors. However, the switching mechanism focused on the formation and rupture of an Ag filament during the SET and RESET, neglecting the contributions of the phase change phenomenon and the distribution and re‐distribution of germanium vacancies defects. The different thicknesses of germanium telluride (GeTe)‐based Ag/GeTe/Pt devices are investigated and the effectiveness of phase loops and defect loops future application in neuromorphic computing are explored. GeTe‐based devices with thicknesses of 70, 100, and 200 nm, are fabricated and their electrical characteristics are investigated. Highly reproducible phase change and defect‐based characteristics for a 100 nm‐thick GeTe device are obtained. However, 70 and 200 nm‐thick devices are unfavorable for the reliable memory characteristics. Upon further analysis of the Ag/GeTe/Pt device with 100 nm of GeTe, it is discovered that a state‐of‐the‐art dependency of phase loops and defect loops exists on the starting and stopping voltage sweeps applied on the top Ag electrode. These findings allow for a deeper understanding of the switching mechanism of monochalcogenide‐based conduction‐bridge memristors.

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ReRAM-Based In-Memory Computing for Search Engine and Neural Network Applications

Cited by 39 publications

References 47 publications

FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Stopping Voltage‐Dependent PCM and RRAM‐Based Neuromorphic Characteristics of Germanium Telluride

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