Reproducible simulation of multi-threaded workloads for architecture design exploration

Pereira, Cristiano; Patil, Harish; Calder, Brad

doi:10.1109/iiswc.2008.4636102

Cited by 10 publications

(3 citation statements)

References 22 publications

(30 reference statements)

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“…Instead, they should write new extensions for the simulator and plug the new extensions into the existing simulator to realize new configurations. This approach can also help support the reproducibility of results, since each module can be clearly defined and reused [46]. DP-3: No magic.…”

Section: Gpu Simulator Design Principlesmentioning

confidence: 99%

MGSim + MGMark: A Framework for Multi-GPU System Research

Baruah¹,

Mojumder²,

Dong³

et al. 2018

Preprint

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The rapidly growing popularity and scale of dataparallel workloads demand a corresponding increase in raw computational power of GPUs (Graphics Processing Units). As single-GPU systems struggle to satisfy the performance demands, multi-GPU systems have begun to dominate the high-performance computing world. The advent of such systems raises a number of design challenges, including the GPU microarchitecture, multi-GPU interconnect fabrics, runtime libraries and associated programming models. The research community currently lacks a publically available and comprehensive multi-GPU simulation framework and benchmark suite to evaluate multi-GPU system design solutions.In this work, we present MGSim, a cycle-accurate, extensively validated, multi-GPU simulator, based on AMD's Graphics Core Next 3 (GCN3) instruction set architecture. We complement MGSim with MGMark, a suite of multi-GPU workloads that explores multi-GPU collaborative execution patterns. Our simulator is scalable and comes with in-built support for multithreaded execution to enable fast and efficient simulations. In terms of performance accuracy, MGSim differs 5.5% on avarage when compared against actual GPU hardware. We also achieve a 3.5× and a 2.5× average speedup in function emulation and architectural simulation with 4 CPU cores, while delivering the same accuracy as the serial simulation.We illustrate the novel simulation capabilities provided by our simulator through a case study exploring programming models based on a unified multi-GPU system (U-MGPU) and a discrete multi-GPU system (D-MGPU) that both utilize unified memory space and cross-GPU memory access. We evaluate the design implications from our case study, suggesting that D-MGPU is an attractive programming model for future multi-GPU systems.

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Section: Gpu Simulator Design Principlesmentioning

confidence: 99%

MGSim + MGMark: A Framework for Multi-GPU System Research

Baruah¹,

Mojumder²,

Dong³

et al. 2018

Preprint

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“…Lepak et al [125] and Pereira et al [156] present approaches to provide reproducible behavior of multithreaded programs when simulating different architecture configurations on execution-driven simulators; whereas Lepak et al consider full-system simulation, Pereira et al focus on user-level simulation. These approaches eliminate non-determinism by guaranteeing that the same execution paths be executed: they enforce the same order of shared memory accesses across simulations by introducing artificial stalls; also, interrupts are forced to occur at specific points during the simulation.…”

Section: Eliminate Non-determinismmentioning

confidence: 99%

Computer Architecture Performance Evaluation Methods

Eeckhout¹

2010

Synthesis Lectures on Computer Architecture

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“…Pin provides an API for writing custom instrumentation, enabling its use in a wide variety of performance analysis tasks such as workload characterization, program tracing, cache modeling, and simulation [11], [15], [18], [19], [26]. Pin is the underlying infrastructure for commercial products like the Intel R Parallel Studio suite of performance analysis tools.…”

Section: Introductionmentioning

confidence: 99%

Dynamic program analysis of Microsoft Windows applications

Skaletsky

Devor

Chachmon

et al. 2010

2010 IEEE International Symposium on Performance Analysis of Systems &Amp; Software (ISPASS)

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Software instrumentation is a powerful and flexible technique for analyzing the dynamic behavior of programs. By inserting extra code in an application, it is possible to study the performance and correctness of programs and systems. Pin is a software system that performs run-time binary instrumentation of unmodified applications. Pin provides an API for writing custom instrumentation, enabling its use in a wide variety of performance analysis tasks such as workload characterization, program tracing, cache modeling, and simulation. Most of the prior work on instrumentation systems has focused on executing Unix applications, despite the ubiquity and importance of Windows applications. This paper identifies the Windows-specific obstacles for implementing a process-level instrumentation system, describes a comprehensive, robust solution, and discusses some of the alternatives. The challenges lie in managing the kernel/application transitions, injecting the runtime agent into the process, and isolating the instrumentation from the application. We examine Pin's overhead on typical Windows applications being instrumented with simple tools up to commercial program analysis products. The biggest factor affecting performance is the type of analysis performed by the tool. While the proprietary nature of Windows makes measurement and analysis difficult, Pin opens the door to understanding program behavior.

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Reproducible simulation of multi-threaded workloads for architecture design exploration

Abstract: Abstract

Cited by 10 publications

References 22 publications

MGSim + MGMark: A Framework for Multi-GPU System Research

MGSim + MGMark: A Framework for Multi-GPU System Research

Computer Architecture Performance Evaluation Methods

Dynamic program analysis of Microsoft Windows applications

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