Reliable and low error dual modular redundancy FIR filter with wide protection window

Wey, I-Chyn; Peng, Chien-Chang; Chou, Heng-Jui; Chen, Po Tsang

doi:10.1587/elex.11.20140183

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Architecture and Circuit Implementations1

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Cited by 4 publications

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“…The FFE shifter register uses three latches for the delay lines. These latches clock with CKP/CKN to shift and generate two discrete-time sequences [25,26,27]. Subsequently, the discrete-time sequence is converted into differential signals and fed to the FFE logic block.…”

Section: Architecture and Circuit Implementationsmentioning

confidence: 99%

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Bai

Zhao

Zuo

et al. 2019

IEICE Electron. Express

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This study presents an 8 Gbps low-power source-series terminated (SST) transmitter for high-speed serial links. The proposed transmitter consists of a novel hybrid 20:2 multiplexer followed by a three-tap feed-forward equalizer (FFE) and a shunt path SST driver. In addition, a high-precision impedance calibration circuit with slice unit replication is proposed to match the characteristic impedance of channel, whose maximum calibration error is 0.002%. Fabricated in 55-nm CMOS technology and has area of 0.024 mm 2 . Measurement results show that the transmitter achieves data rate of 8 Gbps while maintaining good performance. The transmitter has output swing of 510 mV with −6 dB post-tap equalization, and it consumes 15.1 mW under 1.2 V power supply.

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Section: Architecture and Circuit Implementationsmentioning

confidence: 99%