2021
DOI: 10.3390/mi12030295
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Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Abstract: The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the propos… Show more

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Cited by 8 publications
(4 citation statements)
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References 18 publications
(23 reference statements)
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“…With the increasing complexity of packaging structures, manufacturing reliability test vehicles, and conducting ATCT experiments have become time-consuming and very expensive processes, the design-on-experiment (DoE) methodology for packaging design is becoming infeasible. As a result of the wide adoption of finite element analysis [ 9 , 10 , 11 , 12 , 13 , 14 , 15 ], accelerated thermal cycling tests are reduced significantly in the semiconductor industry, and package development time and cost are reduced as well. In a 3D WLP model, Liu [ 16 ] applied the Coffin–Manson life prediction empirical model to predict the reliability life of a solder joint within an accurate range.…”
Section: Introductionmentioning
confidence: 99%
“…With the increasing complexity of packaging structures, manufacturing reliability test vehicles, and conducting ATCT experiments have become time-consuming and very expensive processes, the design-on-experiment (DoE) methodology for packaging design is becoming infeasible. As a result of the wide adoption of finite element analysis [ 9 , 10 , 11 , 12 , 13 , 14 , 15 ], accelerated thermal cycling tests are reduced significantly in the semiconductor industry, and package development time and cost are reduced as well. In a 3D WLP model, Liu [ 16 ] applied the Coffin–Manson life prediction empirical model to predict the reliability life of a solder joint within an accurate range.…”
Section: Introductionmentioning
confidence: 99%
“…However, this advancement has also brought up a significant technical challenge, in which the physical limit of transistor scaling creates enormous difficulties in continuing on the path of Moore’s Law [ 1 ]. In the post-Moore era, the concept of “More than Moore” based on heterogeneous integration using new packaging technologies [ 2 , 3 , 4 , 5 , 6 , 7 , 8 ] is becoming more critical and demanding. Flip-chip chip-scale packaging (FCCSP) possesses the capacity of a high I/O count, miniaturization, and great electrical performance, and thus becomes one of the promising packaging solutions for realizing heterogeneous system integration.…”
Section: Introductionmentioning
confidence: 99%
“…Electrical–thermal responses of vias containing glass interposers, the temperature dissipation ability of Cu-filled via and carbon nano tube(CNT)-filled via were analyzed, and the CNT-filled via showed 30 °C lower temperature compared with the Cu-filled via in [ 32 ]. Different mechanical modeling approaches were utilized to investigate the solder joint reliability of TGV-interposer-based fan-out packaging in [ 33 ]. Warpage characterization of the glass interposer with chemically shrunk epoxy molding compound (EMC) were estimated through experimental and simulation work in [ 34 ].…”
Section: Introductionmentioning
confidence: 99%