Regulating Concurrency in Software Transactional Memory: An Effective Model-based Approach

Sanzo, Pierangelo Di; Re, Francesco Del; Rughetti, Diego; Ciciani, Bruno; Quaglia, Francesco

doi:10.1109/saso.2013.35

Cited by 18 publications

(38 citation statements)

References 16 publications

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“…27 It has been addressed in previous works 7, [11][12][13][14][15][16][17][18][19][41][42][43][44] to dynamically adapt thread parallelism using control techniques for both TM and non-TM systems. 27 It has been addressed in previous works 7, [11][12][13][14][15][16][17][18][19][41][42][43][44] to dynamically adapt thread parallelism using control techniques for both TM and non-TM systems.…”

Section: Parallelism Adaptation With Feedback Controlmentioning

confidence: 99%

“…Feedback control loops have been adopted as cornerstones of software-intensive and self-adaptive systems. 27 It has been addressed in previous works 7,[11][12][13][14][15][16][17][18][19][41][42][43][44] to dynamically adapt thread parallelism using control techniques for both TM and non-TM systems. These works either require offline training procedures to obtain an initial form of a function for parallelism prediction or demand to increment/decrement the thread number progressively in order to search its optimal value.…”

Section: Parallelism Adaptation With Feedback Controlmentioning

confidence: 99%

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An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

Zhou

Delaval

Robu

et al. 2018

Concurrency and Computation

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A parallel program needs to manage the trade-off between the time spent in synchronisation and computation. This trade-off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well-mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time. KEYWORDSautonomic computing, feedback control, parallelism, synchronisation, thread mapping, transactional memory INTRODUCTIONMulti-core processors accelerate computation using high thread parallelism (number of simultaneously active threads). A program for multi-cores executes in parallel and needs to scale when the number of cores increases. However, writing a parallel application is difficult, as parallel programming encompasses all the difficulties of sequential programming and introduces extra problems on coordination of interactions among concurrently executing tasks. 1 High thread parallelism may shorten execution time, but it may potentially increase synchronisation time.Multi-core processors incorporate complex memory hierarchies, which consist of several levels of cache to alleviate penalties caused by the data access to main memory. Consequently, parallel applications need to evolve to efficiently exploit the potential of their underlying architecture.Depending on the level of cache where data are placed, access latency differs from different cores. To alleviate access latency, threads can be fixed to certain cores to improve their resource usage, eg, cache, main memory and interconnections.The conventional way to address synchronisation is via locks. However, locks are notorious for various issues such as deadlocks and the vulnerability to thread failures. 2,3 Furthermore, it is not straightforward to analyse interactions among concurrent operations. Transactional memory (TM) has emerged as an alternative parallel programming technique that handles synchronisation through transactions rather than locks. 4 Access to shared data is enclosed in transactions that are speculatively executed without b...

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Section: Parallelism Adaptation With Feedback Controlmentioning

confidence: 99%

Section: Parallelism Adaptation With Feedback Controlmentioning

confidence: 99%

An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

Zhou

Delaval

Robu

et al. 2018

Concurrency and Computation

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“…The problem of self-tuning TM has also been largely explored in literature, as TM and DTM, unsurprisingly, exhibit similar trade-offs, e.g., the workload characteristics can strongly affect the performance of the concurrency control algorithm, as well as the optimal MPL. Examples of self-tuning solutions that dynamically adjust these TM mechanisms/parameters can be found in [56,57,58,59].…”

Section: Background On Dtmmentioning

confidence: 99%

“…This is the case, for instance, of models that require detailed workload characterization [42] or service demand times [41], and whose measurement from an operational system may introduce prohibitive overheads. This technique is used also in case some parameters of white-box models do not map directly to any physical aspect of the system, and are instead used to encapsulate complex systems' dynamics that would be otherwise hard to capture explicitly via analytical techniques [58]. In these situations, fitting techniques can be used to determine the values of the unknown parameters that minimize the model's prediction errors over a given training set.…”

Section: Which Adaptation To Trigger?mentioning

confidence: 99%

Self-tuning in Distributed Transactional Memory

Couceiro

Didona

Rodrı́gues

et al. 2015

Transactional Memory. Foundations, Algorithms, Tools, and Applications

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Many different mechanisms have been developed to implement Distributed Transactional Memory (DTM). Unfortunately, there is no "one-size-fits-all" design that offers the desirable performance across all possible workloads and scales. In fact, the performance of these mechanisms is affected by a number of intertwined factors that make it hard, or even impossible, to statically configure a DTM platform for optimal performance. These observations have motivated the emergence of self-tuning schemes for automatically adapting the algorithms and parameters used by the main building blocks of DTM systems. This chapter surveys existing research in the area of autonomic DTM design, with a focus on the approaches aimed at answering the following two fundamental questions: how many resources (number of nodes, etc.) should a DTM platform be provisioned with, and which protocols should be used to ensure data consistency.

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“…Didona et al [19] also discuss a similar technique which requires re-architecting and re-implementing application code. Recently [20], [21] have used machine learning and modeling techniques to control concurrency in an application. However, approaches based on offline learning and modeling can degrade significantly with scenarios that challenge the set of assumptions/training data that they rely on and impose an additional burden on the programmers to train the system with appropriate datasets.…”

Section: Related Workmentioning

confidence: 99%

F2C2-STM: Flux-Based Feedback-Driven Concurrency Control for STMs

Ravichandran

Pande

2014

2014 IEEE 28th International Parallel and Distributed Processing Symposium

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Software Transactional Memory (STM) systems provide an easy to use programming model for concurrent code and have been found suitable for parallelizing many applications providing performance gains with minimal programmer effort. With increasing core counts on modern processors one would expect increasing benefits. However, we observe that running STM applications on higher core counts is sometimes, in fact, detrimental to performance. This is due to the larger number of conflicts that arise with a larger number of parallel cores. As the number of cores available on processors steadily rise, a larger number of applications are beginning to exhibit these characteristics.In this paper we propose a novel dynamic concurrency control technique which can significantly improve performance (up to 50%) as well as resource utilization (up to 85%) for these applications at higher core counts. Our technique uses ideas borrowed from TCP's network congestion control algorithm and uses selfinduced concurrency fluctuations to dynamically monitor and match varying concurrency levels in applications while minimizing global synchronization. Our flux-based feedback-driven concurrency control technique is capable of fully recovering the performance of the best statically chosen concurrency specification (as chosen by an oracle) regardless of the initial specification for several real world applications. Further, our technique can actually improve upon the performance of the oracle chosen specification by more than 10% for certain applications through dynamic adaptation to available parallelism.We demonstrate our approach on the STAMP benchmark suite while reporting significant performance and resource utilization benefits. We also demonstrate significantly better performance when comparing against state of the art concurrency control and scheduling techniques. Further, our technique is programmer friendly as it requires no changes to application code and no offline phases.

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Regulating Concurrency in Software Transactional Memory: An Effective Model-based Approach

Cited by 18 publications

References 16 publications

An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

Self-tuning in Distributed Transactional Memory

F2C2-STM: Flux-Based Feedback-Driven Concurrency Control for STMs

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