Register renaming and dynamic speculation: an alternative approach

Abstract

This paper presents a novel microparallel taxonomy for machines with multiple-instruction processing capabilities including V . , superscalar, and decoupled machines. The taxonomy is based upon the static or dynamic behavior of four abstract, operational stages that an instruction passes through. These stages are fetch, decode, execute, and retire. This two valued, four variable taxonomy results in sixteen ways that a processor's microarchitecture can be specifred. This paper categorizes diflerent machine instances that are either actual implementations or proposed system within the taxonomy framework. Four new processor microarchitectures are postulated which provide additional features and are instances of the remaining unexplored m'croparallel class# cations.

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure

“…Delayed physical register allocation was also used in [17] to reduce the conflicts over the write ports in a multiple-banked register file. The second set of techniques aim at reducing the register file pressure by using the early deallocation of physical registers [14,15,16,24,41,45]. In [46], a combination of early deallocation and late allocation was used to completely avoid register allocation for a large number of instructions.…”

“…Researchers have generally exploited the inefficiencies in register usage to reduce the number of registers by using late register allocation [7,19,33], early deallocation [14,15,16,24] and register sharing [4,11,18]. In this paper, we propose alternative mechanisms for reducing the register file pressure.…”

A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

“…Instead, the VB architecture uses a register reclamation strategy based on the counter method [8]. The hardware components used in this scheme, as shown in Fig.…”

Physical register reference counting

“…Registers become free when their reference count reaches zero. These techniques fall into two general classes: ones that use reference counting to track register reads [1,2,6,7,10] and ones that use it to track register "writes" [3,8,9]. Here, we use CPR (Checkpoint Processing and Recovery) [1] and NoSQ (No Store Queue) [9] to represent these two classes, respectively.…”