Register relocation to optimize clock network for multi-domain clock skew scheduling

Yang, Liu; Fan, Baoxia; Cong, Ming; Zhao, Jin

doi:10.1109/iscas.2010.5537941

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…There is an obvious distinction of our flow from traditional flows, which is register clustering and clock skew scheduling are combined and widely used in Godson-3B. An in-house tool [10][11] is developed to generate regular H-trees with clustered registers with precise useful clock skew. The latency of most registers can be adjusted within 200 ps with only cell substitutions of the same size.…”

Section: Sub-module Implementationmentioning

confidence: 99%

Physical Implementation of the Eight-Core Godson-3B Microprocessor

Wang

Fan

Yang³

et al. 2011

J. Comput. Sci. Technol.

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The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6 M transistors within 300 mm 2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS (Globally Asynchronous Locally Synchronous) and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson-3B is maintained by MLMM (Multi Level Multi Mode) clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops (double-precision) or 256 GFlops (single-precision) with 40 W power consumption.

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Section: Sub-module Implementationmentioning

confidence: 99%

Physical Implementation of the Eight-Core Godson-3B Microprocessor

Wang

Fan

Yang³

et al. 2011

J. Comput. Sci. Technol.

Self Cite

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“…Asynchronous FIFO is a first in, first out storage circuit used to store and buffer data transmission between two asynchronous clock domains. Because asynchronous FIFO effectively achieves data buffering while transmitting data to each other, this is an ideal method [1,2].…”

Section: Introductionmentioning

confidence: 99%

Optimizing Data Transfer Across Asynchronous Clock Domains: A Comprehensive Approach to Asynchronous FIFO Circuit Design

Zhang

2024

HSET

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As integrated circuit (IC) design continues to advance in scale, there is a growing trend towards integrating more components onto the same IC board, resulting in larger circuit boards. These expanded circuit boards often encompass diverse asynchronous clock domains, leading to inevitable data transfer challenges between these distinct clock domains. This research article focuses on Verilog-based asynchronous first in first out (FIFO) design as a solution to effectively address this issue and offers a robust design approach to enhance circuit integration and stability. By employing conventional asynchronous FIFO design principles, such as the utilization of binary conversion Gray code to synchronize clock operations for pointer-to-address mapping and the incorporation of empty/full flag status bits to facilitate empty/full signal generation determination, seamless data transfer between various asynchronous clock domains is successfully achieved. Furthermore, this article includes comprehensive testing and simulation using Testbench to validate the asynchronous FIFO circuit, with successful results. The primary objective of this article is to present a well-established and comprehensive design methodology for asynchronous FIFO circuits, equipping designers with a mature and reliable approach to tackle the challenges posed by increasingly complex IC designs.

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Register relocation to optimize clock network for multi-domain clock skew scheduling

Cited by 2 publications

References 16 publications

Physical Implementation of the Eight-Core Godson-3B Microprocessor

Physical Implementation of the Eight-Core Godson-3B Microprocessor

Optimizing Data Transfer Across Asynchronous Clock Domains: A Comprehensive Approach to Asynchronous FIFO Circuit Design

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