Reed-Muller universal logic module networks

Xu, L.; Almaini, A. E. A.; Miller, Julian F.; McKenzie, L.

doi:10.1049/ip-e.1993.0015

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…The use of RM-ULM for realization of logic functions has already been explored by researchers. A programmed algorithm was developed by L. Xu [2], which is analogous to the algorithm in [6], for optimization of number of modules at sub-system level in a tree network. The algorithm looks for possible cascade networks, and if it is not found a tree structure is implemented.…”

Section: Sreela Sasimentioning

confidence: 99%

“…Step 13: Get the reduced piterm tables for each possible (x, ® x;), and find the (x, ® x;) for which both reduced piterm tables are single module implementations by repeating the steps 4 & 5. The exhaustive branching algorithm is demonstrated in the following examples. The delivered network has 3 modules using only 2 levels in the proposed approach, as shown in the Figure 2, while in the tree implementation [2,3] the synthesized network will have 3 modules in 3 levels as shown in Figure 3. Exhaustive branched implementation for F =® L (5,6,9,10) x4 Figure 5.…”

Section: Number Of Zeros > Number Of Ones (Ii)mentioning

confidence: 99%

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Automated synthesis of delay-reduced Reed-Muller universal logic module networks

et al. 2005

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This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.

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Section: Sreela Sasimentioning

confidence: 99%

Section: Number Of Zeros > Number Of Ones (Ii)mentioning

confidence: 99%

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

et al. 2005

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“…There are two types of RM expansions for binary case: the fixed and mixed polarity RM expansions. Expressing a binary function in its mixed polarity RM expansion may possibly yield simpler final circuit design than the fixed counterparts [1,12]. On the other hand, a fixed RM circuit needs only half of the number of inputs as compared to the mixed counterpart.…”

Section: Introductionmentioning

confidence: 99%

A new algorithm to compute quaternary Reed-Muller expansions

Rahardja

Falkowski

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

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A new algorithm to construct a full polarity matrix for n-variable quaternary Reed-Muller expansions has been introduced. The new algorithm directly utilizes the truth vector of the function to construct the polarity matrix. The computational complexity of the algorithm is analyzed and compared with other existing algorithms. It is shown that for n > 6, the new algorithm is computationally more efficient than all existing algorithms. Finally, the fast flow diagram which is useful for implementation of the algorithm in hardware has also been shown.

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Optimization of fixed-polarity Reed-Muller circuits using dual-polarity property

Tan

Yang

2000

Circuits Systems and Signal Process

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Abstract. In the optimization of canonical Reed-Muller (RM) circuits, RM polynomials with different polarities are usually derived directly from Boolean expressions. Time efficiency is thus not fully achieved because the information in finding RM expansion of one polarity is not utilized by others. We show in this paper that two fixed-polarity RM expansions that have the same number of variables and whose polarities are dual can be derived from each other without resorting to Boolean expressions. By repeated operations, RM expansions of all polarities can be derived. We consequently apply the result in conjunction with a hypercube traversal strategy to optimize RM expansions (i.e., to find the best polarity RM expansion). A recursive route is found among all possible polarities to derive RM expansion one by one. Simulation results are given to show that our optimization process, which is simpler, can perform exhaustive search as efficiently as other good exhaustive-search methods in the field.

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Reed-Muller universal logic module networks

Cited by 8 publications

References 7 publications

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

A new algorithm to compute quaternary Reed-Muller expansions

Optimization of fixed-polarity Reed-Muller circuits using dual-polarity property

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