Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Starecek, L.; Sekanina, Lukáš; Kotásek, Zdenĕk

doi:10.1109/ddecs.2008.4538796

Cited by 6 publications

(2 citation statements)

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“…In particular, we plan to employ REPOMO32 in the area of circuit diagnostics and security. The "second" function provided by polymorphic gates can be activated in test mode of a circuit in order to detect faults [11] or reduce the number of test vectors [10], [16]. In the area of security, polymorphic gates can implement "invisible" functions which can be activated under special conditions.…”

Section: B Potential Applicationsmentioning

confidence: 99%

“…This gate exhibits a very unconventional structure; in particular, it does not follow the wellaccepted rules for transistor-level design of CMOS gates. Then, researchers have begun to develop the methods for polymorphic circuits synthesis and integrate the polymorphic gates to various digital circuits to enhance their functionality [10], [11], [12], [13], [14], [15], [16]. Almost exclusively, the experiments were done using simulators.…”

Section: Introductionmentioning

confidence: 99%

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REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware

Sekanina

Růžička

Vašíček

et al. 2009

2009 IEEE Workshop on Evolvable and Adaptive Hardware

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In this paper, a new reconfigurable polymorphic chip (REPOMO32) is introduced. This chip has been developed in order to investigate the electrical properties of polymorphic circuits and demonstrate the applications of polymorphic electronics. REPOMO32 contains an array of 32 configurable logic elements; each of them can perform the AND, OR, XOR and polymorphic NAND/NOR function which is controlled by the level of the power supply voltage. REPOMO32 parameters are reported together with the analysis of polymorphic circuits implemented and evolved in REPOMO32. Potential applications of the chip are also discussed.

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Section: B Potential Applicationsmentioning

confidence: 99%