Reducing the power consumption of two-dimensional logic transistors

Abstract

The growing demand for high-performance logic transistors has driven the exponential rise in chip integration, while the transistors have been rapidly scaling down to sub-10 nm. The increasing leakage current and subthreshold slope (SS) induced by short channel effect (SCE) result in extra heat dissipation during device operation. The performance of electronic devices based on two-dimensional (2D) semiconductors such as the transition metal dichalcogenides (TMDC) can significantly reduce power consumption, benefiting from atomically thin thickness. Here, we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors (MOSFETs) and 2D negative capacitance field effect transistors (NCFETs), outlining their potential in low-power applications as a technological option beyond scaled logic switches. Above all, we show our perspective at 2D low-power logic transistors, including the ultra-thin equivalent oxide thickness (EOT), reducing density of interface trap, reliability, operation speed etc. of 2D MOSFETs and NCFETs.

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf0.5Zr0.5O2 Thin Films

“…Generally, the MOSFET is operated at high frequency, and we checked the operating dynamics of the FeFET (see Section 8 in the Supporting Information). Compared with the standalone MOSFET, the FeFET turns on with a delay time, which can be caused by ferroelectric polarization switching dynamics and charge redistribution − (Figure S11 in the Supporting Information). The turn-on speed is fast for the large ferroelectric capacitance (i.e., the large diameter d ) or the large V DS , which can be attributed to an increase in the rate of charge accumulation caused by ferroelectric polarization switching (Figure S12 in the Supporting Information).…”

Controlling the Polarity of WSe2 FETs by Interface Engineering for High-Gain CMOS

“…Generally, a channel material should possess suitable mobility, band gap, and the ability to control the polarity of logic circuit integration. Tungsten diselenide (WSe 2 ) is found to be a highly promising 2D semiconductor material for its applications in transistors via experiments and theoretical calculations. , However, due to the limitation of the device integration process, the reported performance of WSe 2 -based FETs is below the theoretical value, and achieving controlled polarity regulation remains a challenge.…”

Ultra‐Steep‐Slope High‐Gain MoS2 Transistors with Atomic Threshold‐Switching Gate

“…[ 1 , 2 ] However, subthreshold swing (SS) is fundamentally limited to above 60 mV dec −1 at room temperature, because of Boltzmann distribution of carrier, which leads to exponential growth of leakage current and static power consumption. [ 3 ] Therefore, reducing SS has become one of the critical challenges for large‐scale high‐performance integrated circuit development. [ 4 ] Several steep‐slope devices based on innovative structure or transport mechanisms, such as tunnel FETs (TFETs) [ 5 , 6 ] and negative capacitance FETs (NCFETs), [ 7 ] have been proposed to combat the “Boltzmann tyranny,” which have SS below 60 mV dec −1 at room temperature.…”