Reducing test application time through test data mutation encoding

Abstract

In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits that need to be flipped in the current test data slice in order to obtain the mutated subsequent test data slice. Exploitation of the overlap in the encoded data by effective traversal search algorithms results in drastic overall compression. The technique we propose can be utilized as not only a stand-alone technique but also can be utilized on test data already compressed, extracting even further compression. The performance of the algorithm is mathematically analyzed and its merits experimentally confirmed on the larger examples of the ISCAS'89 benchmark circuits.

High-Quality Statistical Test Compression With Narrow ATE Interface

“…Even though both the ATPG and fault simulation steps can be straightforwardly embedded in both the LPDR method and the proposed encoding, we omitted these steps as they cannot be applied in the case of IP cores (their internal structure is unknown). We also compare our method to various code-based methods [5], [6], [47], and [25]. For all methods we use the minimum number of ATE channels, that is one channel for the proposed method and code-based methods, and two channels for LPDR (a very small number of channels is highly desirable in a multi-site test environment).…”

“…Even for the test cube at hand, which consists of 33.3% specified bits and is rather densely specified, there are many CVs that can be used, like for example 000100001001, 000100000011, 000100100101, etc. (as shown in many studies [20], [25], the vast majority of test cubes of industrial designs consists of less than 5% of specified test bits). Each different CV implies a different merging process.…”

“…The methods in [6], [47], and [25] focus on test time and TDV optimization and method [15] is a TDC method that targets average power reduction too. In the case of the proposed method we set the value of parameters l = 8, P = 0, and a = 0.0625.…”

Virtual compression through test vector stitching for scan based designs

“…The long scan chain is broken into multiple shorter partitions, while a decompression network either on the circuit under test or on the ATE is used to decode test vectors to the multiple scan chain partitions. Through the test compression approach presented by Reda and Orailoglu [5], test appli- cation time and test data is compressed by encoding the bits that need to be flipped, thus attaining high compression ratios yet at the cost of decompression hardware insertion. An alternative approach attempts to find as many overlaps between test vectors, thus obtaining test data compression [6].…”

Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression

“…Other techniques are based on on-chip pattern decompression, such as scan-chain concealment [15], geometric-primitive based compression [16], mutation encoding [17], deterministic embedded test (reusing the scan chain of one core in a SoC to compress the patterns for another core) [18], packet-based compression [19] and LFSR reseeding [2] [20] [21]. An embedded deterministic test technology for low cost test to reduce the scan test data volume and scan test time is presented in [22].…”