2000
DOI: 10.1109/4.848208
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Reducing MOSFET 1/f noise and power consumption by switched biasing

Abstract: Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical efect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 14 noise. The technique is implemented in a 0 . 8 p CMOS sawtooth oscillator by periodically of-switching of the bias currents during time intervals that theyare not contributing to the circuit operation. Measurements show a reduction of the lynoise induced phase noise by more than 8 dB, while the power consumption is reduc… Show more

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Cited by 227 publications
(118 citation statements)
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References 19 publications
(8 reference statements)
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“…Dynamically switching the bias of MOS devices will reduce their flicker noise, as also demonstrated in [3]. It also lessens the DC component of their effective impulse sensitivity function.…”
Section: Switching Current Source Oscillatormentioning
confidence: 85%
“…Dynamically switching the bias of MOS devices will reduce their flicker noise, as also demonstrated in [3]. It also lessens the DC component of their effective impulse sensitivity function.…”
Section: Switching Current Source Oscillatormentioning
confidence: 85%
“…The PSD of an RTS is given by (5); the same holds for the effective stationary RTS, the time constants of which were are given by (9).…”
Section: E Generalisation To Trap Distributionmentioning
confidence: 99%
“…The switched biasing technique (Figure 2) reduces the 1/ noise of a MOS transistor by cyclically increasing and decreasing its gate bias so that the device alternates between strong inversion and accumulation [22]. The transistor noise is modulated by the switching signal.…”
Section: Clock-based Techniques the Noise In Cmos Transistorsmentioning
confidence: 99%