Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization

Abstract

Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay and energy requirement of driving the result tags across the associatively-addressed issue queue accounts for a significant percentage of the scheduler's overhead and also limits the design scalability. We propose two schemes to reduce the power consumption and the delays of the wakeup logic. Our first scheme-instruction packing-shares the associative part of an issue queue entry between two instructions, each with at most one non-ready source. As a result, the number of entries in the issue queue (and, hence, the length of the tag buses) can be reduced by a factor of two with almost no impact on the IPCs, because most instructions either enter the pipeline with at least one of their source operands ready, or do not make use of two source registers to begin with. Our second scheme-tag memoizationavoids driving the upper portion of the tags, if those bits did not change their values from what was driven on the same tag bus during the most recent broadcast. While instruction packing results in the reduced length of the tag buses, tag memoization reduced the number of tag lines that need to be driven. We evaluate our designs using detailed microarchitectural simulations of the SPEC 2000 benchmarks and the SPICE simulations of the issue queue layouts.

Exploiting Operand Availability for Efficient Simultaneous Multithreading

“…In practice, the maximum number of instructions held by this scheduler is often less than 64 because some instructions occupy fullsized entries. Note further that this terminology is different from that used in our previous work [34], [35].…”

“…In this section, we briefly describe instruction packing as proposed for superscalar machines in [34], [35] to provide sufficient background for the rest of the paper. Fig.…”

“…To exploit this idle tag CAM, instruction packing [34], [35] shares one issue queue entry between two such instructions. With instruction packing, an entry in the IQ can hold one or two instructions, depending on the number of ready operands in the stored instructions at the time of dispatch.…”

“…More details describing this technique can be found elsewhere [34], [35]. In the next section, we discuss the application of instruction packing to SMT processors and show that it is an even more effective technique for those machines.…”

“…To this end, we propose several solutions. First, we extend the previously introduced instruction packing mechanism [34], [35] to SMT. Instruction packing opportunistically places two instructions into the same IQ entry provided that each of these instructions has at most one nonready source operand at the time of dispatch.…”