Rectification of multiple logic design errors in multiple output circuits

Tomita, Masahiro; Yamamoto, T.; Sumikawa, Fuminori; Hirano, Kyoko

doi:10.1145/196244.196356

Cited by 43 publications

(12 citation statements)

References 15 publications

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“…These approaches can be divided into two categories with respect to the underlying technique used for error location and error correction: those based on Boolean function manipulation (symbolic) techniques [8]- [11], [16]- [18], [24], [27], [32] and those based on test vector simulation [13]- [15], [21], [22], [25], [26], [28], [29], [33], [34].…”

Section: A Previous Workmentioning

confidence: 99%

“…In addition, existing work shows that test vector simulation can be a computationally efficient route to DEDC for designs corrupted with one and two errors. However, just like the symbolic methods, their performance decreases as the number of errors increases, and little work [26], [28], [29] has been performed on design error correction for the complete error model of Abadir et al [2].…”

Section: A Previous Workmentioning

confidence: 99%

“…For diagnosis, the method performs an implicit enumeration of error lines in an effort to avoid the exponential explosion of the error space (1) and remain computationally efficient. In detail, unlike most previous test vector simulationbased approaches [13]- [15], [22], [25], [26], [28], [33], [34], it does not attempt to explicitly compute the complete error space and eliminate areas that cannot contain an error(s). Instead, it samples and searches a small area of the error space for error candidates.…”

Section: B Work Overviewmentioning

confidence: 99%

“…It should be noted that the space of potential erroneous lines grows exponentially in the number of errors [26] error line space of circuit lines of errors (1) It can also be seen that the correction space for a design where modifications are selected from the model of Abadir et al [2] is lower bounded by the error line space.…”

mentioning

confidence: 99%

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Design error diagnosis and correction via test vector simulation

Veneris

Hajj

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.

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Section: A Previous Workmentioning

confidence: 99%

Section: A Previous Workmentioning

confidence: 99%

Section: B Work Overviewmentioning

confidence: 99%

mentioning

confidence: 99%

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Design error diagnosis and correction via test vector simulation

Veneris

Hajj

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…For example, the golden model can be a Matlab program while the design is in Verilog. This complicates the debugging effort dramatically because the solution space explodes exponentially to the number of errors in the design [21]:…”

Section: What Is Debugging?mentioning

confidence: 99%

The day Sherlock Holmes decided to do EDA

Veneris

Safarpour

2009

Proceedings of the 46th Annual Design Automation Conference

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Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and budgetary constraints. A fundamental aspect of the design process that remains primitive is that of debugging. It takes months to close, it introduces costs and it may jeopardize the release date of the chip. This paper reviews the debugging problem and the research behind it over the past 20 years. The case for automated RTL debug tools and methodologies is also made to help ease the manual burden and complement current industrial verification practices.

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