Figure 8. Single-electron transistors (SETs). a) Schematic structure and b) transfer I-V characteristic of a typical SET. c) Schematic diagram and scanning electron microscopy image of the two-gate SET. d) Transfer I-V characteristic of the two-gate SET at V in2 = 0 V and 0.2 V. c,d) Reproduced with permission. [18] Copyright 2000, IEEE. e) Circuit diagram of the universal literal gate and its periodic V in −V out characteristic. Reproduced with permission. [98] Copyright 2003, IEEE. f) Schematic of the two-input hybrid MOSFET-SET device. g) The output voltage as a function of two input gate voltages. f,g) Adapted with permission. [103] Copyright 2009, IEEE. h,i) Schematic diagram of the Si EQD SET (h) and its typical two-peak transfer characteristic (i). j) Contour plot demonstrating I D as a function of V DS and V G enabling ternary and quaternary operation regimes. h-j) Reproduced with permission. [105]