Reconfigurable Hardware Implementation of the Successive Overrelaxation Method

Abstract

2Reconfigurable Hardware Implementation of the SOR Method the system at hand. There are two basic approaches for solving linear systems: Direct Methods and Iterative Methods. In the first approach, a finite number of operations are performed to find the exact solution. In the second approach, an initial approximate of the solution is generated, then this initial guess is used to generate another approximate solution, which is more accurate than the previous one [12] The robustness of applying iterative methods over direct methods is shown in different areas including: circuit analysis and design, weather forecasting and analyzing financial market trends.The well-known iterative methods are: Gauss-Seidel, Multigrid, Jacobi and Successive Over-Relaxation (SOR) which is of a interest in this chapter. SOR has been devised to accelerate the convergence of Gauss-Seidel and Jacobi [13], by introducing a new parameter, , referred to as the relaxation factor. The SOR rate of convergence is highly dependent on the relaxation factor. The main difficulty of using SOR is finding a good estimate of the relaxation factor [12]. Several techniques have been proposed for determining the exact value of which accelerates the rate of convergence of the method [12,13].All available iterative methods packages, including SOR, are done in software. Examples are the: ITPACK 3A, ITPACK 3B, ITPACK 2C, ITPACK 2D, and the ELLPACK package [14,15]. Several sequential and parallel techniques were used in these packages to accelerate the method [16].The emergence of the new computing paradigm, Reconfigurable Computing (RC), introduces novel techniques for accelerating certain classes of applications including signal processing (e.g., weather forecasting, seismic data processing, Magnetic Resonance Imaging (MRI), adaptive filters), cryptography and DNA matching [17]. RC-systems combine the flexibility offered by software and the performance offered by hardware [18]. It requires a reconfigurable hardware, such as an FPGA, and a software design environment that aids in the creation of configurations for the reconfigurable hardware [17].In [19], the first hardware implementation of an iterative method-the Multigridis presented. The speedup achieved demonstrates that hardware design can be suited for such computationally intensive applications. Toward proving the hypothesis that accelerated versions of the iterative methods can be realized in hardware, we undertook the first hardware implementation of the SOR method; using the same FPGAs that were used in [19][20][21].In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware. We use Handel-C, a higher-level design tool to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i and Quartus II 5.1). We target Virtex II Pro, Altera Stratix and Spartan3L which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them ...