Real-time fault-tolerance with hot-standby topology for conditional sum adder

a b s t r a c tIn the complex computing system, processing units are dealing with devices of smaller size, which are sensitive to the transient faults. A transient fault occurs in a circuit caused by the electromagnetic noises, cosmic rays, crosstalk and power supply noise. It is very difficult to detect these faults during offline testing. Hence an area efficient fault tolerant full adder for testing and repairing of transient and permanent faults occurred in single and multi-net is proposed. Additionally, the proposed architecture can also detect and repair permanent faults. This design incurs much lower hardware overheads relative to the traditional hardware architecture. In addition to this, proposed design also provides higher error detection and correction efficiency when compared to the existing designs. Ó 2016 The Authors. Publishing services by Elsevier on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

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“…The hardware cost of the proposed and self repairing adder can be calculated and compared using the Eq. (9) [30].…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

Real-time fault tolerant full adder design for critical applications

Kumar

Sharma

2016

Engineering Science and Technology, an International Journal

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“…So far, many fault-tolerant fixed-point arithmetic operators or units have been designed such as [7][8][9][10][11][12]. However, the fault-tolerant floating-point arithmetic units have received less attention.…”

Section: Related Workmentioning

confidence: 99%

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

Mohajer¹,

Valinataj²

2017

IJMECS

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Abstract-This paper presents a new fault-tolerant architecture for floating-point multipliers in which the fault-tolerance capability is achieved at the cost of output precision reduction. In this approach, to achieve the faulttolerant floating-point multiplier, the hardware cost of the primary design is reduced by output precision reduction. Then, the appropriate redundancy is utilized to provide error detection/correction in such a way that the overall required hardware becomes almost the same as the primary multiplier. The proposed multiplier can tolerate a variety of permanent and transient faults regarding the acceptable reduced precisions in many applications. The implementation results reveal that the 17-bit and 14-bit mantissas are enough to obtain a floating-point multiplier with error detection or error correction, respectively, instead of the 23-bit mantissa in the IEEE-754 standardbased multiplier with a few percent area and power overheads.

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“…Afterwards, offspring are created considering Eqs. (11) and (12). Figure 6 elaborates the process of the crossover operator for the 1 th row of chromosomes.…”

Section: Cga Operatorsmentioning

confidence: 99%

“…The situation that all components are operated simultaneously from the time zero is called active redundancy versus standby redundancy that the redundant components are used sequentially during component failure times [7]. Moreover, standby redundancy is categorized into three different types, namely, cold [8][9][10], hot [11,12], and warm [13][14][15] so that frees the component to fail before it operates in the cold standby redundancy versus warm standby that components are more likely to be failed before operating. Further, the failure pattern of components is freed from the idleness or the operation of the components with respect to the hot standby redundancy.…”

Section: Introductionmentioning

confidence: 99%

A note on a reliability redundancy allocation problem using a tuned parameter genetic algorithm

et al. 2015

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This paper presents an improved continuous genetic algorithm (CGA) to optimize the reliability redundancy allocation problem (RRAP) which determines the best redundancy strategies, the number of components, and levels of each subsystem to maximize the system reliability. In this system, both active and cold-standby redundancies can be chosen for individual subsystems. The RRAP belongs to NP-hard problems in the computational complexity theory that is the main reason for employing CGA to solve it. In addition, the response surface methodology (RSM) is used to increase the performance of CGA considering the design of experiments. This algorithm employs a new chromosome so that frees offspring to repair during the evolution process. Considering several numerical examples, the proposed algorithm presents better solutions than the previous studies based on the system reliability. Finally, the conclusion and future research are considered.

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Real-time fault-tolerance with hot-standby topology for conditional sum adder

Cited by 29 publications

References 23 publications

Real-time fault tolerant full adder design for critical applications

Real-time fault tolerant full adder design for critical applications

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

A note on a reliability redundancy allocation problem using a tuned parameter genetic algorithm

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