Racetrack memory cell array with integrated magnetic tunnel junction readout

Annunziata, Anthony; Gaidis, M. C.; Thomas, Luc; Chien, Chun-Hsien; Hung, Chin-Hsien; Chevalier, P.; O’Sullivan, E. J.; Hummel, John P.; Joseph, Eric; Zhu, Yu; Topuria, Teya; Delenia, E.; Parkin, S. S. P.; Gallagher, W. J.

doi:10.1109/iedm.2011.6131604

Cited by 74 publications

(47 citation statements)

References 5 publications

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“…The nanowire can be built in 3D or 2D, the latter one is easier to be fabricated and become the mainstream solution for the current research on this topic. Based on in-plane magnetic anisotropy, the first racetrack memory prototype was presented in 2011 by IBM despite of its small capacity 256 bits [56]. However the intrinsic low energy barrier separating the two in-plane magnetization directions of storage layer leads to short data retention in advanced technology node (e.g., 22 nm) [51].…”

Section: Racetrack Memorymentioning

confidence: 99%

Current-Induced Magnetic Switching for High-Performance Computing

Zhang

Zhao

Wang

et al. 2015

Spintronics-Based Computing

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Section: Racetrack Memorymentioning

confidence: 99%

Current-Induced Magnetic Switching for High-Performance Computing

Zhang

Zhao

Wang

et al. 2015

Spintronics-Based Computing

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“…The experimental results on spin valves, magnetic-tunnel junctions (MTJ), domain wall memory (DWM) etc. [12][13][14][15][16][17][18] have created enormous interest in spin based computations. The most promising effect is current induced modulation of magnetization dynamics discovered in MTJ and DWM as it opens door to energy-efficient logic and memory design.…”

Section: B Types Of Pufsmentioning

confidence: 99%

“…DWM is a flavor of magnetic memory that provides the above benefits due to its ability to store multiple bits per bitcell for high-density [12][13][14]. Additionally, it provides low standby power (due to non-volatility), fast access, good endurance and retention [15].…”

Section: A Brief Introductionmentioning

confidence: 98%

DWM-PUF: A low-overhead, memory-based security primitive

Iyengar

Ramclam

Ghosh

2014

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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Physically Unclonable Function (PUF) is a security primitive to address hardware security issues such as chip authentication, Intellectual Property (IP) protection etc. Conventional CMOS PUFs are built on delay (inverter chains, scan chains etc.) or memory structures (like SRAM). In this paper, we propose a novel PUF which works on the principles of spintronic Domain Wall Memory (DWM). Conventional DWM is limited by pinning due to process variations induced surface roughness of the nanowire. We exploit this limitation towards chip-authentication. We propose two flavors of PUFs namely relay-PUF and memory-PUF. The proposed PUFs show excellent entropy (measured by Hamming Distance). We also analyze metrics such as robustness, area and power of the DWM-PUFs. The memory-PUF indicated up to an order of magnitude reduction in power compared to SRAM PUF.

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“…A racetrack memory array contains of many magnetic strips (or racetracks), each of which is integrated with magnetic storage pillars (or magnetic domains). The area of a magnetic domain can be as small as only 1F 2 [14]. Since the size of access transistors cannot scale down accordingly, a racetrack can be connected to only a few access transistors.…”

Section: Introductionmentioning

confidence: 99%

The evolutionary spintronic technologies and their usage in high performance computing

Sun

2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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This paper gives a comprehensive summary of our study in using the spintronic technologies for the on-chip cache density improvement of high performance computing systems. We will start with the spin-transfer torque random access memory (STT-RAM) at the early of stage of commercialization and then extend it to the emerging racetrack memory that has been successfully demonstrated at device and small array level. In multi-level cell (MLC) STT-RAM cache, the cell design constrains, e.g., the switching current requirement and asymmetry in write operations, severely limit the density benefit. Moreover, the twostep read/write accesses and inflexible data mapping strategy may even result in system performance degradation. This paper will discuss our circuit and architecture combined solution. Advanced spintronic technology, i.e., racetrack memory, enables an extremely high storage density and offers a faster-thanMoores law scaling path. Unorthodox new memory hierarchies are necessary to minimize the impact of pseudo-sequential accesses of racetrack memory.

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Racetrack memory cell array with integrated magnetic tunnel junction readout

Cited by 74 publications

References 5 publications

Current-Induced Magnetic Switching for High-Performance Computing

Current-Induced Magnetic Switching for High-Performance Computing

DWM-PUF: A low-overhead, memory-based security primitive

The evolutionary spintronic technologies and their usage in high performance computing

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