Qubit Bias using a CMOS DAC at mK Temperatures

Otten, René; Schreckenberg, L.; Vliex, P.; Ritzmann, Julian; Ludwig, Arne; Wieck, Andreas D.; Bluhm, Hendrik

doi:10.1109/icecs202256217.2022.9971043

Cited by 4 publications

(1 citation statement)

References 12 publications

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“…3,4) Using interposers is a promising route to evade the need for full single-chip integration of all functionalities. [5][6][7][8] However, thermal stability down to cryogenic temperatures is a warranted concern when transferring this established technology at room temperature to cryogenic silicon qubit experiments. Although both the interposer chip and quantum dot (QD) devices are typically made of silicon, there is a possibility of coefficient of thermal expansion mismatch between the metallic bumps and the silicon chips at cryogenic temperature.…”

Section: Introductionmentioning

confidence: 99%

Cryogenic flip-chip interconnection for silicon qubit devices

Futaya,

Mizokuchi,

Taguchi

et al. 2024

Jpn. J. Appl. Phys.

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Interfacing qubits with peripheral control circuitry poses one of the major common challenges toward realization of large-scale quantum computation. Spin qubits in silicon quantum dots are particularly promising for scaling up, owing to the potential benefits from the know-how of the semiconductor industry. In this paper, we focus on the interposer technique as one of the potential solutions for the quantum-classical interface problem and report DC and RF characterization of a silicon quantum dot device mounted on an interposer. We demonstrate flip-chip interconnection with the qubit device down to 4.2 K by observing Coulomb diamonds. We furthermore propose and demonstrate a laser-cut technique to disconnect peripheral circuits no longer in need. These results may pave the way toward system-on-a-chip quantum-classical integration for future quantum processors.

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Section: Introductionmentioning

confidence: 99%

Cryogenic flip-chip interconnection for silicon qubit devices

Futaya,

Mizokuchi,

Taguchi

et al. 2024

Jpn. J. Appl. Phys.

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Spin-EPR-pair separation by conveyor-mode single electron shuttling in Si/SiGe

Struck,

Volmer,

Visser

et al. 2024

Nat Commun

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Long-ranged coherent qubit coupling is a missing function block for scaling up spin qubit based quantum computing solutions. Spin-coherent conveyor-mode electron-shuttling could enable spin quantum-chips with scalable and sparse qubit-architecture. Its key feature is the operation by only few easily tuneable input terminals and compatibility with industrial gate-fabrication. Single electron shuttling in conveyor-mode in a 420 nm long quantum bus has been demonstrated previously. Here we investigate the spin coherence during conveyor-mode shuttling by separation and rejoining an Einstein-Podolsky-Rosen (EPR) spin-pair. Compared to previous work we boost the shuttle velocity by a factor of 10000. We observe a rising spin-qubit dephasing time with the longer shuttle distances due to motional narrowing and estimate the spin-shuttle infidelity due to dephasing to be 0.7% for a total shuttle distance of nominal 560 nm. Shuttling several loops up to an accumulated distance of 3.36 μm, spin-entanglement of the EPR pair is still detectable, giving good perspective for our approach of a shuttle-based scalable quantum computing architecture in silicon.

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The SpinBus architecture for scaling spin qubits with electron shuttling

Künne,

Willmes,

Oberländer

et al. 2024

Nat Commun

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Quantum processor architectures must enable scaling to large qubit numbers while providing two-dimensional qubit connectivity and exquisite operation fidelities. For microwave-controlled semiconductor spin qubits, dense arrays have made considerable progress, but are still limited in size by wiring fan-out and exhibit significant crosstalk between qubits. To overcome these limitations, we introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Device simulations for all relevant operations in the Si/SiGe platform validate the feasibility with established semiconductor patterning technology and operation fidelities exceeding 99.9%. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits. Building on the theoretical feasibility of high-fidelity spin-coherent electron shuttling as key enabling factor, the SpinBus architecture may be the basis for a spin-based quantum processor that meets the scalability requirements for practical quantum computing.

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Qubit Bias using a CMOS DAC at mK Temperatures

Cited by 4 publications

References 12 publications

Cryogenic flip-chip interconnection for silicon qubit devices

Cryogenic flip-chip interconnection for silicon qubit devices

Spin-EPR-pair separation by conveyor-mode single electron shuttling in Si/SiGe

The SpinBus architecture for scaling spin qubits with electron shuttling

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