Progress and future challenges of SiC power devices and process technology

Kimoto, Tsunenobu; Niwa, H.; Kaji, Noritada; Kobayashi, Takuma; Zhao, Yuanfu; Mori, Seigo; Aketa, Masatoshi

doi:10.1109/iedm.2017.8268360

Cited by 17 publications

(10 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Kimoto et al have reported that the sub-bands are shifted upward with increasing the p-body doping, leading to a stronger quantum confinement effect. [34] Thus, the energy levels of D it of the NO annealed sample exhibits a sharp increase toward (and likely inside) the conduction band edge in SiC. Therefore, the mobility of NO annealed sample on a more heavily doped p-body, affected by a higher D it located at higher energy levels, drops significantly in heavily-doped MOSFETs.…”

Section: Sic Mosfet Characterizationmentioning

confidence: 96%

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation*

Liu¹,

Hao²,

You³

et al. 2020

Chinese Phys. B

View full text Add to dashboard Cite

The microwave plasma oxidation under the relatively high pressure (6 kPa) region is introduced into the fabrication process of SiO2/4H-SiC stack. By controlling the oxidation pressure, species, and temperature, the record low density of interface traps (∼ 4 × 1010 cm−2⋅eV−1@Ec − 0.2 eV) is demonstrated on SiO2/SiC stack formed by microwave plasma oxidation. And high quality SiO2 with very flat interface (0.27-nm root-mean-square roughness) is obtained. High performance SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with peak field effect mobility of 44 cm−2 ⋅eV−1 is realized without additional treatment. These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.

show abstract

Section: Sic Mosfet Characterizationmentioning

confidence: 96%

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation*

Liu¹,

Hao²,

You³

et al. 2020

Chinese Phys. B

View full text Add to dashboard Cite

show abstract

“…Silicon carbide (SiC) exhibits excellent properties, such as high critical breakdown field strength, high thermal conductivity, and high electron saturation velocity compared to Si material [1,2]. Thus, SiC MOSFET has comparative advantages over Si-MOSFET in terms of switching speed, junction temperature operation, and energy loss enabling a significant improvement in energy density and reduced weight and the volumetric ratio [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm

Chen

Yan

Ibrahim³

et al. 2023

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

As the next generation of semiconductor devices, SiC MOSFETs have demonstrated significant performance improvements in switching loss, switching frequency, and hightemperature operation compared to Si-based MOSFETs. However, the long-term reliability of such devices and their packaging continues to be a major concern. Towards addressing this challenge, this study proposes a multi-objective optimization design method for parasitic inductance (L), thermal strain (ε), and thermal resistance (R) of SiC MOSFETs with Fan-Out Panel-Level Packaging (FOPLP). First, the orthogonal experimental design was employed to investigate the thickness effects of baseplate, solder, die and redistribution layer (RDL) on L, ε, and R. Then, the multiobjective optimization was developed to simultaneously reduce L, ε, and R. Finally, the fatigue lifetimes of the optimized and initial SiC MOSFET FOPLP structures were compared to verify the optimization's accuracy. Study findings include: (1) Solder thickness was the most significant influence factor for L, ε and R of SiC MOSFET FOPLP, L and R increased, and ε decreased with increasing solder thickness; (2) The proposed multi-objective optimization method coupled with a genetic algorithm achieved 14.79, 8.96, and 9.28% reduction of L, ε, and R, respectively; (3) The fatigue lifetime of solder (SAC305) was evaluated using the Coffin-Manson model, with predicted lifetimes before and after optimization being 6786 and 7085 cycles, respectively, demonstrating that the proposed approach significantly enhanced the designed SiC MOSFET FOPLP's long-term thermal cycling reliability.

show abstract

“…The reliability of silicon carbide (SiC) devices deserves serious attention from device designers on account of the fact that SiC devices are generally designed to operate at high voltage/current conditions in harsh environments [ 1 , 2 , 3 , 4 , 5 , 6 , 7 ]. Surge current capability, which represents the ruggedness of power devices under high current pulses, is one of the key indices of the device reliability [ 8 , 9 , 10 , 11 , 12 ], for the reason that high current pulses are common at the starting-up of electrical equipment or during accidental circuit failures.…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Silicon Carbide Merged PiN Schottky Diodes with Electrical-Thermal Coupled Considerations

Ren

Guo

et al. 2020

Materials

View full text Add to dashboard Cite

A comparative study of surge current reliability of 1200 V/5 A 4H-SiC (silicon carbide) MPS (Merged PiN Schottky) diodes with different technologies is presented. The influences of device designs in terms of electrical and thermal aspects on the forward conduction performance and surge current capability were studied. Device forward characteristics were simulated and measured. Standard single-pulse surge current tests and thermal impedance measurements were carried to show their surge capability and thermal design differences. An advanced thermal RC (thermal resistance-capacitance) model, with the consideration of current distribution non-uniformity effects, is proposed to accurately calculate the device junction temperature during surge events. It was found that a thinner substrate and a hexagonal layout design are beneficial to the improvement of the bipolar conduction performance in high current mode, as well as the surge current capability. The thinner substrate design also has advantages on thermal aspects, as it presents the lowest thermal resistance. The calculated failure temperature during the surge tests is consistent with the aluminum melting phenomenon, which is regarded as the failure mechanism. It was demonstrated that, for a SiC MPS diode, higher bipolar conduction performance is conducive to restraining the joule heat, and a lower thermal resistance design is able to accelerate the heat dissipation and limit the junction temperature during surge events. In this way, the MPS diode using a thinner substrate and advanced layout design technology is able to achieve 60% higher surge current density capability compared to the other technologies.

show abstract

Progress and future challenges of SiC power devices and process technology

Cited by 17 publications

References 12 publications

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation*

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation*

Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm

A Comparative Study of Silicon Carbide Merged PiN Schottky Diodes with Electrical-Thermal Coupled Considerations

Contact Info

Product

Resources

About