Programming and Timing Analysis of Parallel Programs on Multicores

Abstract

Abstract-Multicore processors provide better powerperformance trade-offs compared to single-core processors. Consequently, they are rapidly penetrating market segments which are both safety critical and hard real-time in nature. However, designing time-predictable embedded applications over multicores remains a considerable challenge. This paper proposes the ForeC language for the deterministic parallel programming of embedded applications on multicores. ForeC extends C with a minimal set of constructs adopted from synchronous languages. To guarantee the worst-case performance of ForeC programs, we offer a very precise reachabilitybased timing analyzer. To the best of our knowledge, this is the first attempt at the efficient and deterministic parallel programming of multicores using a synchronous C-variant. Experimentation with large multicore programs revealed an average over-estimation of only 2% for the computed worstcase execution times (WCETs). By reducing our representation of the programs state-space, we reduced the analysis time for the largest program (with 43, 695 reachable states) by a factor of 342, to only 7 seconds.

Sequentially Constructive Concurrency—A Conservative Extension of the Synchronous Model of Computation

“…PRET-C [Andalam et al 2009] also provides determinate reactive control flow; however, PRET-C assumes fixed priorities per thread and thus could not execute SC programs that require back-and-forth context switching between threads. Even more restrictive is the synchronous approach ForeC [Yip et al 2013] for multicore execution which does not permit any communication during a tick at all. SHIM [Tardieu and Edwards 2006] provides concurrent Kahn process networks with CSP-like rendezvous communication [Hoare 1985] and exception handling.…”

Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times

“…A number of low-level reaction time analysis techniques already exist [Bertin et al 2001;Wilhelm et al 2008]. Note that these techniques have already studied incorporating communicating latencies for instance, shared memory via time division multiplexing, [Yip et al 2013] and hence, the reaction time includes these latencies. A real-time analyzable execution platform, which guarantees bounded execution times for native instructions by removing the source of uncertainties (such as data caches and branch predictions, etc.…”

The ForeC Synchronous Deterministic Parallel Programming Language for Multicores

“…This section begins by evaluating the static worst-case reaction time (WCRT) analysis of ForeC programs. We have previously shown [18] that the WCRT of ForeC programs could be estimated to a high degree of precision, which is very useful for implementing real-time embedded systems. Further, we provide a performance comparison between ForeC and Esterel.…”

“…Once the embedded system is implemented, the synchrony hypothesis is validated by ensuring that the WCET of any global tick does not exceed the minimal inter-arrival time of the inputs. This is known as worst-case reaction time analysis and techniques have been developed for multi-cores [17], [18]. C-based synchronous languages, such as PRET-C [19] and SyncCharts in C [20], appeal to C programmers because the learning barrier for synchronous languages is reduced.…”