PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs

Abstract

Leveraging partial reconfiguration (PR) can improve system flexibility, cost, and performance/power/area tradeoffs over non-PR functionally-equivalent systems, however, realizing these benefits is challenging, time-consuming, and PR must be considered early during application design to reduce design exploration time and improve system quality. To facilitate realizing these benefits, we present an application design framework and an abstract modeling language for PR (PRML). By applying extensive PRML modeling guidelines to a complex arithmetic core, we show PRML's potential for efficient PR capability analysis, enabling designers to determine Pareto optimal systems during application formulation based on designer-specified area and performance metrics.

An Automated High-Level Design Framework for Partially Reconfigurable FPGAs

“…However, since CLaSH is a highly specialized language, CLaSH has not been widely adopted. In prior work [11], we alleviated the requirement of a highly specialized language using a simple graph modeling technique to model an application's algorithm. Our work partitioned the graph model using PR-specific partitioning techniques to create all potential PR architectures.…”

“…Figure 1 presents an overview of PaRAT's methodology. PaRAT evaluates the application's HLS source code written in VIVADO-HLS-synthesizable C, and parses and analyzes this code using an in-house, heavily modified gcc-python-plugin [12] to generate a PRML model [11], which captures the application's control and data dependencies, and partitions the PRML model to create the static modules and PRMs (PRspecific partitioning). To enable PR design space exploration, PaRAT generates per-module HLS code from the application's HLS code, which are automatically synthesized using VIVADO-HLS to identify per-module area and longest path delay values to facilitate PR design space exploration.…”

“…PRML [11] provides extensive guidelines, nodes, edges, and per-node and per-edge attributes to model an application. To avoid loopback edges and to facilitate PR-specific partitioning, PRML guidelines ensure that PRML models are always directed acyclic graphs.…”

“…PaRAT evaluates an application's C-based HLS source code to capture the application's control and data dependence information. We represent the control and data dependence information using a partial reconfiguration model language (PRML) model similar to [11], but significantly enhanced to include nested dependencies. We partition this PRML model based on the PRspecific partitioning technique in [11], but our work enumerates all static module and PRM combinations, which enables complete exploration of the PR architecture design space.…”

“…We represent the control and data dependence information using a partial reconfiguration model language (PRML) model similar to [11], but significantly enhanced to include nested dependencies. We partition this PRML model based on the PRspecific partitioning technique in [11], but our work enumerates all static module and PRM combinations, which enables complete exploration of the PR architecture design space. PaRAT quickly estimates the PR architectures' areas and clock frequencies using the VIVADO-HLS tool [17], which enables comparative evaluation of the PR architectures' tradeoffs with respect to system design goals.…”