Preparation, Characterization, and Damage-Free Processing of Advanced Multiple-Gate FETs

Lauerhaas, Jeffrey M.; Cleavelin, R.; Xiong, Wei; Mochizuki, K.; Sherman, Kara; Lee, Hu Cheng; Clappin, Brian; Schulz, T.; Schruefer, K.

doi:10.4028/www.scientific.net/ssp.134.213

Cited by 5 publications

(3 citation statements)

References 5 publications

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“…Increasing fin height may cause internal damage and operational failure due to massive internal stress on a narrow base, causing fracture and leading to operational failure. [37][38][39] So, for 3 nm, 5 nm, 7 nm gate lengths, we have considered tri-gate geometry 40 with L G = F W = F H and compared with 10 nm FinFET. Scaling 10 nm FinFET with tri-gate geometry at lower L G with dielectric spacers induces better DIBL and SS with both D-k spacer combinations.…”

Section: Resultsmentioning

confidence: 99%

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Sreenivasulu

Narendar

2021

ECS J. Solid State Sci. Technol.

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In this paper, we have studied the impact of various dielectric single-k (S-k) and dual-k (D-k) spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric oxide based (HfxTi1−xO2) gate stack to enhance the sub-threshold performance of the device. Performance impact of outer low-k spacer variation on D-k spacer by fixing inner high-k spacer has been reported. In this move, it is noticed that the I ON/I OFF ratio shifted from 8.70 × 105 to 1.30 × 106 which is about ∼1.5x times improvement. Along with DC characteristics, analog/RF and linearity metrics are extracted and analysed. Due to a better gate electrostatic integrity (EI) at an extremely scaled L G , an optimally designed D-k spacer reveals a better DC and analog performance characteristics. The S-k spacer reveals a better performer in power consumption, dynamic power, RF, and linearity characteristics at nano scale. Furthermore, the scaling possibilities by spacers on DC and Analog performance at L G = 10 nm FinFET with tri-gate geometry at L G of 7 nm, 5 nm, and 3 nm are also examined. It has been noticed that the enhanced performance with the tri-gate structure is best suitable for future technological nodes.

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Section: Resultsmentioning

confidence: 99%

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Sreenivasulu

Narendar

2021

ECS J. Solid State Sci. Technol.

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“…However, manufacturing challenges and associated mechanical stresses are major concerns with taller fin devices. With increasing AR ( H fin / W fin ), the height may concentrate larger internal stresses in their relatively narrow base, causing fracture and in turn operational failure [ 24 ].…”

Section: Design and Analysis Of Rf/analogy Performance Of Asymd-kkmentioning

confidence: 99%

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit

et al. 2017

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Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (gm) and output conductance (gds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (fT) and maximum oscillation frequency (fmax) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kkDE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.

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“…Additionally, as the device dimensions are scaled, process-induced changes in the fins and oxide thickness become more pronounced, adversely affecting the device-to-device variability and deteriorating the mismatch parameter. [17][18][19] Further, the researchers also developed an ultra shallow junction (USJ) in order to restrain the propagation of the lateral electric field into the channel region. Nonetheless, the development of USJ is controlled by several factors such as junction leakage, temperatures, cost-effectiveness, defect formation, process control, etc.…”

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confidence: 99%

Design Considerations into Circuit Applications for Structurally Optimised FinFET

Sarangam,

Valasa,

Mudidhe

et al. 2023

ECS J. Solid State Sci. Technol.

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FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (Lg), fin width (Wfin) and fin height (Hfin) for the duak-k spacer FinFET is performed and it is found that lowering the Lg and Wfin, and increasing the Hfin would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.

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Preparation, Characterization, and Damage-Free Processing of Advanced Multiple-Gate FETs

Cited by 5 publications

References 5 publications

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit

Design Considerations into Circuit Applications for Structurally Optimised FinFET

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