Practical exact synthesis

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused primarily on graphs with 2-input nodes such as AND and OR gates, the recently proposed paradigm of Majority-Inverter Graphs instead uses the 3-input Majority gate as the node function. As this technique proved to be a success, it is natural to ask: Are there other 3-input gates better suited for logic synthesis? Motivated by this question, we investigate the relative advantages of 3-input gates as constituents of logic networks. We consider representative gates from each of the ten non-degenerate 3-input NPN classes and study how powerful they are at representing Boolean functions. Using SAT-based exact synthesis, we evaluate each 3-input gate using the minimum number of such gates (together with inverters) needed to synthesize all 4-input Boolean functions and a subset of frequent 5-input and 6-input Boolean functions. We show that the logic gate Dot(x, y, z) := x ⊕ (z ∨ x y) outperforms the rest in terms of expressive power. We further confirm this observation by showing that Dot-Inverter Graph representations are more than 14% smaller as compared to Majority-Inverter Graph representations of EPFL benchmarks.

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“…We now introduce SAT-based exact synthesis as presented in [12], [13], [15], and show how it is applied to synthesize 3-input gate networks.…”

Section: Sat-based Exact Synthesismentioning

confidence: 99%

Three-Input Gates for Logic Synthesis

Marakkalage

Testa

Riener

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Let us note that di®erent structure encodings can be used, e.g., as shown in Ref. 35. In principle, di®erent encodings o®er a trade-o® between the instance size and its \simplicity" for SAT-solvers.…”

Section: The Cnf Constructionmentioning

confidence: 99%

“…A SAT-based approach producing delay-optimal solutions is presented in Ref. 35. In principle, a similar approach is adopted; the delays of each node are represented by bitstrings.…”

Section: Deriving Depth-optimal Implementationsmentioning

confidence: 99%

SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support

Fišer

Háleček

Schmidt

et al. 2019

J CIRCUIT SYST COMP

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This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one or enumerate all optimum implementations, while the allowed target gate types and gates costs can be arbitrarily specified. Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable of performing two or more different intended functions, depending on instantaneous conditions in the target operating environment. In this paper we propose the first method ever, generating provably size-optimal polymorphic circuits. Scalability and feasibility of the method are documented by providing experimental results for all NPN-equivalence classes of four-input functions implemented in AND–Inverter and AND–XOR–Inverter logics without polymorphic behavior support being used and for all pairs of NPN–equivalence classes of three-input functions for polymorphic circuits. Finally, several smaller benchmark circuits were synthesized optimally, both in standard and polymorphic logics.

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“…Such a high complexity makes exact synthesis algorithms not practical, either while considering the number of logic gates or design logic depth. Though recent efforts have been made towards the multi-level logic exact synthesis (SOEKEN et al, 2018)(SOEKEN et al, 2017, it is still constrained by functions with a few inputs, and the proposed methods may be suitable to use in tandem with larger non-exact logic synthesis algorithms. Therefore, the majority of current logic synthesis algorithms are heuristic.…”

Section: Logic Synthesismentioning

confidence: 99%

“…Such a custom block may comprise a function whose circuit was exactly synthesized. It can be done with exact synthesis methods that run over small functions (SOEKEN et al, 2018)(SOEKEN et al, 2017)(HAASWIJK et al, 2018. Also, exact benchmarks proposed in (CONG;MINKOVICH, 2007) and in could be adopted as custom blocks.…”

Section: Embedding Custom Logic Into Ilbmentioning

confidence: 99%

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation

Neto

Possani

Marranghello

et al. 2018

2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)

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To my family, in special to my parents Richard and Claudia, my aunt Nelza and my grandmother Astrid thank you for supporting me in my studies. To my uncle Sérgio and my aunt Maria Candida thank you for receiving me in your home when I moved to Porto Alegre, in 2011. Thanks to that I could have the opportunity to come to study here. Also, I would like to thank my brother, Nicholas, who has tolerated to share an apartment with me in the last years. To my advisor, Renato Ribas, thank you for the patience and the valuable lessons. In particular, I would like to thank you for the discussions about life in general. Even though the technical knowledge is essential, many times it may be found in books and, in our area, tends to become deteriorated in a short time. However, the kind of lessons I have learned from you about research and life will remain with me forever. Also, I would like to thank professor André Reis for trusting on me and giving me opportunities to improve my knowledge. Furthermore, I would like to thank my colleagues (friends) from LogiCS labs. Thank you for receiving me so well. I am grateful for all of our discussions, funs, barbecues and soccer. In the scope of this work, I would like to thanks Felipe Marranghello, for discussing reversible logic with me from the beginning of my studies, as well as Vinicius Possani for always explaining me the concepts of logic synthesis and algorithms. To my friends from PUCRS and GAPH thanks for the discussions and fun we have had during these years. Special thanks to Alexandre Amory who has introduced me to the research and to Matheus Moreira who has taught me a lot and is a great friend. Finally, to all my friends thank you for understanding when I could not go somewhere because of my studies. Also, thanks for all the funny moments we have had.

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Practical exact synthesis

Cited by 19 publications

References 21 publications

Three-Input Gates for Logic Synthesis

Three-Input Gates for Logic Synthesis

SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation

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