Power gating scheduling for power/ground noise reduction

Jiang, Hailin; Marek-Sadowska, Malgorzata

doi:10.1145/1391469.1391716

Cited by 32 publications

(13 citation statements)

References 9 publications

(8 reference statements)

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“…To keep the overhead of the additional regulator low, the sizes of the off-chip capacitors can be reduced significantly because each regulator handles a smaller current load in the new design. Each core in the CMP can be dynamically assigned to either of the two power rails using gating circuits [17,22] that allow very fast transition between the two voltage levels. Within each core, only a single power distribution network is needed, leaving the core layout unchanged.…”

Section: Core-level Fast Voltage Switchingmentioning

confidence: 99%

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Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Miller

Pan

Thomas

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process variation, which can lead to large differences in the maximum frequency achieved by individual cores. This paper presents Booster, a simple, low-overhead framework for dynamically rebalancing performance heterogeneity caused by process variation and application imbalance. The Booster CMP includes two power supply rails set at two very low but different voltages. Each core can be dynamically assigned to either of the two rails using a gating circuit. This allows cores to quickly switch between two different frequencies. An on-chip governor controls the timing of the switching and the time spent on each rail. The governor manages a "boost budget" that dictates how many cores can be sped up (depending on the power constraints) at any given time. We present two implementations of Booster: Booster VAR, which virtually eliminates the effects of core-to-core frequency variation in near-threshold CMPs, and Booster SYNC, which additionally reduces the effects of imbalance in multithreaded applications. Evaluation using PARSEC and SPLASH2 benchmarks running on a simulated 32-core system shows an average performance improvement of 11% for Booster VAR and 23% for Booster SYNC.

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Section: Core-level Fast Voltage Switchingmentioning

confidence: 99%

“…The Booster CMP includes two power supply rails set at two very low but different voltages. Each core in the CMP can be dynamically assigned to either of the two power rails using a gating circuit [17]. This allows each core to rapidly switch between two different maximum frequencies.…”

Section: Introductionmentioning

confidence: 99%

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Miller

Pan

Thomas

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

View full text Add to dashboard Cite

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“…It alleviates the switching activity induced resonant P/G noise by controlling instruction access to reduce simultaneous switching activities in the pipeline. Jiang et al proposed a scheduling technique to address system-level power gating with several gated blocks and optimize the wake up order of these blocks in terms of noise [17]. It tries to alleviate the rush current during the power gating of heterogeneous blocks by optimizing their wakeup schedule, and reduces the power gating induced P/G noise with increased wake up time.…”

Section: Related Workmentioning

confidence: 99%

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuitlevel MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.

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“…Power gating cuts both leakage and dynamic power by disconnecting idle blocks from the power grid. This technique has been extensively studied and can be implemented efficiently at coarse (FU) granularity [13].…”

Section: Additional Hardware Neededmentioning

confidence: 99%