Power-efficient simulation of detailed cortical microcircuits on SpiNNaker

Sharp, T. G.; Galluppi, Francesco; Rast, Alexander; Furber, Steve

doi:10.1016/j.jneumeth.2012.03.001

Cited by 48 publications

(60 citation statements)

References 37 publications

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“…Large-scale implementations of Izhikevich neurons have been previously implemented in software, using computing clusters consisting of high-performance/high-powerconsuming general purpose processors [12], lower power fixed-point processors [13], FPGAs [14] and GPUs [15].…”

Section: Design Considerationsmentioning

confidence: 99%

Neural spiking dynamics in asynchronous digital circuits

Imam

Wecker

Tse

et al. 2013

The 2013 International Joint Conference on Neural Networks (IJCNN)

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Abstract-We implement a digital neuron in silicon using delay-insensitive asynchronous circuits. Our design numerically solves the Izhikevich equations with a fixed-point number representation, resulting in a compact and energy-efficient neuron with a variety of dynamical characteristics. A digital implementation results in stable, reliable and highly programmable circuits, while an asynchronous design style leads to energy-efficient clockless neurons and their networks that mimic the event-driven nature of biological nervous systems. In 65 nm CMOS technology at 1 V operating voltage and a 16-bit word length, our neuron can update its state 11,600 times per millisecond while consuming 0.5 nJ per update. The design occupies 29,500 µm 2 and can be used to construct dense neuromorphic systems. Our neuron exhibits the full repertoire of spiking features seen in biological neurons, resulting in a range of computational properties that can be used in artificial systems running neural-inspired algorithms, in neural prosthetic devices, and in accelerated brain simulations.

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Section: Design Considerationsmentioning

confidence: 99%

Neural spiking dynamics in asynchronous digital circuits

Imam

Wecker

Tse

et al. 2013

The 2013 International Joint Conference on Neural Networks (IJCNN)

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“…One plausible metric can be the unit energy consumption for a single spiking. Such a metric can be found in [17], [18].…”

Section: Energy Consumption Estimationmentioning

confidence: 99%

“…IBM did not provide the energy statistic for their BlueGene simulator [19]. Nevertheless, [18] provides an estimate that it "consumes 655kW to simulate 1.6 · 10 9 neurons at the speed of 643 second per Hz." So the energy per spiking-event is 655 · 10 3 * 643/(1.6 · 10 9 ) = 263.6mJ/s.e.…”

Section: Energy Consumption Estimationmentioning

confidence: 99%

“…The SpiNNaker system, which uses a multicore ARM system with customized interconnection, consumes 43nJ/s.e. [18]. On the other end, IBM's crossbar-based ASIC implementation consumes 45pJ/s.e.…”

Section: Energy Consumption Estimationmentioning

confidence: 99%

“…The SpiNNaker project combines a general-purposed multicore ARM system with customized interconnection, and offers great improvement in energy efficiency [27], [28] compared to large-scale HPC implementation. However, using general-purposed cores as computing units for neuron simulation is still not efficient, especially when neuron simulation often consists of very simple operations with limited precision.…”

Section: Related Workmentioning

confidence: 99%

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FPGA simulation engine for customized construction of neural microcircuits

Blair

Cong

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.

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A Marr's Three‐Level Analytical Framework for Neuromorphic Electronic Systems

Guo

Zou

et al. 2021

Advanced Intelligent Systems

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Neuromorphic electronics, an emerging field that aims for building electronic mimics of the biological brain, holds promise for reshaping the frontiers of information technology and enabling a more intelligent and efficient computing paradigm. As their biological brain counterpart, the neuromorphic electronic systems are complex, having multiple levels of organization. Inspired by David Marr's famous three‐level analytical framework developed for neuroscience, the advances in neuromorphic electronic systems are selectively surveyed and given significance to these research endeavors as appropriate from the computational level, algorithmic level, or implementation level. Under this framework, the problem of how to build a neuromorphic electronic system is defined in a tractable way. In conclusion, the development of neuromorphic electronic systems confronts a similar challenge to the one neuroscience confronts, that is, the limited constructability of the low‐level knowledge (implementations and algorithms) to achieve high‐level brain‐like (human‐level) computational functions. An opportunity arises from the communication among different levels and their codesign. Neuroscience lab‐on‐neuromorphic chip platforms offer additional opportunity for mutual benefit between the two disciplines.

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Power-efficient simulation of detailed cortical microcircuits on SpiNNaker

Cited by 48 publications

References 37 publications

Neural spiking dynamics in asynchronous digital circuits

Neural spiking dynamics in asynchronous digital circuits

FPGA simulation engine for customized construction of neural microcircuits

A Marr's Three‐Level Analytical Framework for Neuromorphic Electronic Systems

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