Power‐efficient, PVT robust conductance cancellation method for gain enhancement

Abstract

A power-efficient, process, voltage and temperature (PVT) robust g ds cancellation method for gain enhancement is proposed. The method generates a negative conductance, which matches and cancels the positive conductance. This makes the g ds cancellation method effective over process and wide temperature variation without the aid of external calibration or a tuning circuit. The method senses signals from cascode nodes instead of output nodes, making the method insensitive to output voltage swing. The simulation results of an example implementation in IBM 0.13 µm process show at least 22 dB DC gain enhancement over all process corners and temperatures ranging from − 20 to 80°C, with less than 9% power consumption overhead.

Calibration of the Nauta structure differential OTA

“…The schematic of the implementation can be seen in Figure 11. In Table 7 [18] it can be seen that this method achieves comparable performance to the method propose in [17] while the design procedure was simplified significantly. This highlights the need for easily implementable and easy to design solutions that can ideally be implemented in various technologies without much effort.…”

“…the matching between g d1s2 and g n , and therefore high gain can be maintained under process and temperature variation. The method proposed in [17] improves the gain of a conventional structure by at least 22dB when tested across all process corners in 130nm technology as seen in Table 6.…”

“…Another method was proposed in [17], where it was attempted to eliminate the need for manual tuning and propose a technique that performed equally well across all process corners. This method also uses the conductance, in this case the output conductance, g ds12 of transistor M12, rather than the transconductance of an element to generate a negative output conductance and makes this approach more robust when it comes to process and temperature variation.…”

“…The output cancelation concept proposed in [17] was further explored and improved in [18] in order to simplify the design and reduce the number of required simulations. The design method was simplified to a point where essentially only the sizing of a single transistor needs to be considered.…”

“…Based on the gathered data, a synthesisable digital calibration algorithm is then presented. Table 1 - Table 7 -Performance Comparison of Conventional Amplifier and the Ones Examined in [17] and [18]…”