Power Consumption and Performance Analysis of 3D NoCs

Sharifi, Akbar; Sarbazi-Azad, Hamid

doi:10.1007/978-3-540-74309-5_21

Cited by 2 publications

(2 citation statements)

References 13 publications

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“…The paper [9] analyzes in detail the performance of NOC including its power consumption. In the present study our attention was focused on dynamic capacitive power consumption considered as the main part of energy losses in CMOS circuits.…”

Section: Physical-level Low-power Implementationmentioning

confidence: 99%

Heterogeneous NoC Physical-Level Low-Power Implementation

Zhang

2008

2008 International Conference on Internet Computing in Science and Engineering

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A heterogeneous network-on-chip (NoC) is presented and implemented focusing on low-power communication in various design levels such as circuits, signaling, channel coding for possible application to energy-efficient NoC design. It incorporates heterogeneous intellectual properties (IPs) interconnected in a hierarchical star topology, and provides integrated IPs, which operate at different clock frequencies, with packet-switched serialcommunication infrastructure. Physical level-oriented low-power implementation is devised, and applied to achieve the power-efficient on-chip communications.

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Section: Physical-level Low-power Implementationmentioning

confidence: 99%

Heterogeneous NoC Physical-Level Low-Power Implementation

Zhang

2008

2008 International Conference on Internet Computing in Science and Engineering

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“…Virtual channel implementation consumes a lot of buffer and suffers from starvation for some NoC applications [31]. Besides, such routers suffer from large area and power consumption [32]. A study of the area and energy benefits of combining 2D and 3D routers in 3D mesh and torus topologies is presented in [11].…”

Section: Optimized Heterogeneous 3d Noc Architecturesmentioning

confidence: 99%

A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

Agyeman¹

2015

IJCA

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Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This paper presents a brief about 3D NoCs optimization techniques with focus on modeling and evaluation of alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, we investigate novel 3D NoC router architectures and their possible combinations which aim at achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off.

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Power Consumption and Performance Analysis of 3D NoCs

Cited by 2 publications

References 13 publications

Heterogeneous NoC Physical-Level Low-Power Implementation

Heterogeneous NoC Physical-Level Low-Power Implementation

A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

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