Power and performance exploration of embedded systems executing multimedia kernels

Dasygenis, Minas; Kroupis, N.; Tatas, K.; Argyriou, Antonios; Soudris, Dimitrios; Thanailakis, A.

doi:10.1049/ip-cdt:20020468

Cited by 12 publications

(15 citation statements)

References 9 publications

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“…Specifically, power consumption is related to the number of memory transfers, which is the dominant factor of total power cost, and this motivated the researchers to find efficient techniques to reduce it. For that purpose, a data memory hierarchy that exploits the temporal locality of the data, by reusing them, was suggested [3,5,16,17]. If there is a sufficient reuse of the data elements, it can be advantageous to copy the frequently-used data to a smaller memory, so that successive requests of this data element can be read from a smaller memory instead of a larger one.…”

Section: Introductionmentioning

confidence: 98%

“…The smaller memories require less power per access and, as a result, the total power consumption can be reduced drastically [21]. In case, the target architecture is a programmable processor, the total memory power consumption consists of two components [17]: i) the energy consumption due to data memory transfer, and ii) the energy consumption due to instruction memory transfers. The array signals dominate mainly the data memory transfers and the memory size for storing them.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Kroupis

Zervas²,

Dasygenis

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs.

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Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Kroupis

Zervas²,

Dasygenis

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

show abstract

“…Landman's energy model has been used in [6], [14], [21], which is parameterized by the capacitances and the frequencies of read and write operations. Several power models exist for cache [5], which are based on the estimate of the cache line hit rate and several hardware-related parameters.…”

Section: Proposed Power Modelmentioning

confidence: 99%

“…Brockmeyer et al [13] refine the memory assignment and placement involved in [6] with the low energy objective. The effects of different combinations of data reuse transformations and memory system structures on the system power consumption and performance have been shown in [14] and [15] for platforms with multiple embedded instruction set processors.…”

Section: Introductionmentioning

confidence: 99%

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Liu

Constantinides

Masselos

et al. 2009

IET Comput. Digit. Tech.

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Contemporary FPGA-based reconfigurable systems have been widely used to implement data dominated applications. In these applications data transfer and storage consume a large proportion of the system energy. Exploiting data reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data reuse design exploration early during the design cycle, we present an optimization approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data reuse exploration problem is mathematically formulated and shown to be equivalent to the Multiple-Choice Knapsack Problem (MCKP). The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happens in the code, in order to minimize power consumption for a fixed on-chip memory size. We also present an experimentally verified power model, capable of providing the relative power information between different data reuse design options of an application, resulting in a fast and efficient design space exploration. The experimental results demonstrate that the approach enables us to find the most power efficient design for all the benchmark circuits tested.

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“…However, no systematic formulation is proposed for this combined optimization. In [23] and [24], the authors experiment with the effects of different data-reuse transformations and memory system architectures on the system performance and power consumption. The results prove the necessity of the exploration of data reuse and data-level parallelization.…”

Section: Introductionmentioning

confidence: 99%

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

Liu

Constantinides

Masselos

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called geometric programming problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performanceoptimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times.

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Power and performance exploration of embedded systems executing multimedia kernels

Cited by 12 publications

References 9 publications

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

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