Post-layout logic restructuring for performance optimization

Abstract

We propose a new methodology based on incremental logic restructuring for post-layout performance improvement. The new post-layout logic restructuring technique allows to use accurate interconnection delays for performance optimization, while the incremental nature of the technique guarantees convergence between logic synthesis and layout. The technique can be further integrated with other post-layout optimization techniques such as gate sizing and buffer insertion. Experimental results show that this technique combined with post-layout buffer insertion can achieve an additional 15% improvement in performance compared to designs produced by timing-driven logic optimization followed by pre-layout buffer insertion followed by timing-driven physical design. IntroductionPerformance-driven logic synthesis followed by performance-driven layout [1] has become a necessity for designing high performance circuits. However, this loosely coupled two-phase timing optimization methodology has serious limitations for deep-submicron-based designs in which interconnection delays become the dominant factor in determining the circuit speed. Accurate information regarding the interconnection delays is not available during the logic synthesis phase and the interconnection delays are just roughly estimated in this phase. Therefore, errors in the estimation could result in a logic design far-off from an optimal one.Recently, an ATPG-based approach, named Redundancy Addition and Removal, was proposed for combinational and synchronous sequential logic optimization [3][4] [5]. This approach optimizes the networks through iterative addition and removal of redundant connections. The redundancy addition and removal technique can identify alternative connections or gates for any given connection. For performance optimization, we can remove a connection on a critical path and replace it by one of its alternative connections/gates not on the critical path. Since

Minimization of the expected path length in BDDs based on local changes

“…Moreover, the resulting BDDs are also minimized in average gate delay and hence are a good starting point for additional critical path analysis [12,3,14]: it is well-known that these techniques can further improve the results by subsequent local reorganization, up to optimizing the delay on a critical path to not exceed the average delay at all [2].…”

Cycle time optimization by timing driven placement with simultaneous netlist transformations

“…Recently, several approaches to improve the interaction between logic synthesis and physical design have been published [2,9,11,[14][15][16].…”

“…In this case the wire lengths are estimated from the placement. The other possibility is to apply the transformations in a routed design with all wire lengths known [9].…”

“…Jiang et al [9] proposed a method for post-layout performance improvement. They start with a complete circuit layout.…”

“…Additionally, after each transformation a legalization step is necessary to correct the layout. For this legalization step ECO-algorithms [9] or other placement improvement algorithms [15] are used.…”