“…[ 17 ] Moreover, previously reported work indicated that trap states mainly located at the interfaces of multilayers of whole device (called interface defects) and at the perovskite surface (called surface defects), which are effectively related to the energy level matching, hysteresis, charge carriers dynamics, and the long‐term environmental and operational stability. [ 18–22 ] Therefore, it is indispensable to explore an impressive way to diminish the defects, particularly at the interfaces, for acquiring the high‐efficient and stable PSCs. Currently, there are lots of approaches to improve the performance and stability of PSCs, containing additive engineering, using additive into a perovskite absorber layer and interface engineering, modifying the hole transport layer (HTL)/perovskite or perovskite/electron transport layer (ETL) interfaces.…”