Performance-driven interconnect design based on distributed RC delay model

Cong, Jason; Leung, Kwok-Shing; Zhou, Dian

doi:10.1145/157485.165065

Cited by 144 publications

(139 citation statements)

References 11 publications

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“…It was shown in [20] that when the resistance ratio, defined to be the driver effective resistance over the unit wire resistance, is small enough, both the total wirelength (i.e. the total interconnect capacitance) and interconnect topology will impact the interconnect delay.…”

Section: B Interconnect Topology Optimizationmentioning

confidence: 99%

“…Other algorithms in this class include the AHHK tree construction and the 'performance oriented spanning tree' construction, which are discussed in [22] and [3]. In particular, it was shown in [20] that a minimal length shortest path tree in the Manhattan plane (called the A-tree) can be constructed very efficiently using a bottom-up merging heuristic with sizable delay reduction yet only a small wire-length overhead compared to the OST. The A-tree construction method has been extended to signal nets with multiple drivers (as in signal busses) [23].…”

Section: B Interconnect Topology Optimizationmentioning

confidence: 99%

“…It was first shown in [20,29] that when wire resistance becomes significant, as in the deep submicron design, proper wire-sizing can effectively reduce the interconnect delay. Assuming each wire has a set of discrete wire widths, their work presented an optimal wiresizing algorithm for a single-source RC interconnect tree to minimize the sum of weighted delays from the source to timing-critical sinks under the Elmore delay model.…”

Section: E Wiresizing Optimizationmentioning

confidence: 99%

“…It naturally combines the A-tree construction algorithm [20] and the simultaneous buffer insertion and wiresizing algorithm [30], as both use bottom-up construction techniques. The WBA algorithm includes a bottom-up synthesis procedure and a topdown selection procedure.…”

Section: F2 Simultaneous Topology Construction With Buffer and Wirementioning

confidence: 99%

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Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: B Interconnect Topology Optimizationmentioning

confidence: 99%

Section: B Interconnect Topology Optimizationmentioning

confidence: 99%

Section: E Wiresizing Optimizationmentioning

confidence: 99%

Section: F2 Simultaneous Topology Construction With Buffer and Wirementioning

confidence: 99%

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Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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“…We construct two different trees to implement the same net in figure 1. The constructed trees are shown in figure 7, where treel is a minimum Steiner tree and tree2 is an A-tree [14]. Traditionally, treel is considered as the optimal implementation which provides the minimal delay under the lumped RC model.…”

Section: Waveform Delay and Design Examplementioning

confidence: 99%

A Simplified Synthesis of Transmission Lines with a Tree Structure

Zhou¹,

Su²,

Tsui³

et al. 1994

Modeling and Simulation of High Speed VLSI Interconnects

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Abstract. The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributed RLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in an RLC tree. The result on the RLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.

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RT-Level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime

Durbha,

Katkoori

2000

VLSI: Systems on a Chip

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As the interconnect dominates in DSM regime, we propose a novel routeand-place design methodology at RT-Ievel which strongly ties to physical design tasks. Unlike conventional place-and-route, our methodology prioritizes interconnect over devices. At the RT-Ievel, we identify all global nets and carefully design their interconnect topology to achieve desired delay characteristics, followed by the macro-cell placement. Net clustering is carried out to account for net interdependencies as weil as to derive the bounding box constraint on a net. Within a macro-cell, as the nets are local in nature, we apply place-and-route to achieve its layout. Experimental results on various datapath circuits resulted in total wirelength reduction varying from 3.7% to 24.6% with an average value of 12.4%.

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Performance-driven interconnect design based on distributed RC delay model

Cited by 144 publications

References 11 publications

Interconnect design for deep submicron ICs

Interconnect design for deep submicron ICs

A Simplified Synthesis of Transmission Lines with a Tree Structure

RT-Level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime

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