Performance degradation due to thicker physical layer of high k oxide in ultra-scaled MOSFETs and mitigation through electrostatics design

Salmani-Jelodar, Mehdi; Kim, SungGeun; Ng, Kwok K.; Klimeck, Gerhard

doi:10.1109/snw.2014.7348567

Cited by 4 publications

(4 citation statements)

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“…2-A shows the results for the configuration I, without interface layer and with no gate leakage assumption. As expected, the thicker oxide would degrade the device performance by increasing the sub-threshold swing (SS) and lowering ON-current for the fixed OFF-current [6]. However, when gate tunneling is included, in the SiO 2 case, the OFF-current rises above 100 nA/um.…”

Section: Methodsmentioning

confidence: 82%

“…As it is depicted in Fig. 3-D DIBL improves by a reduction in the oxide thickness [6], but for very thin oxides, higher gate leakage slows down the DIBL value reduction [9]. Thin T OX improves the gate control over the channel (or top of the barrier), which results in weaker drain control over the channel.…”

Section: Methodsmentioning

confidence: 99%

“…Thicker T OX from larger k values worsen the short channel effects, even if the EOT is kept the same [4]. This happens due to the effect of the lateral field in the oxide, which is more pronounced in higher k materials [4,5], and fringing capacitance due to spread of potential between the gate and the source and drain [6]. It is known that not only EOT, but also the physical oxide thickness plays important roles in SCEs.…”

mentioning

confidence: 99%

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Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Salmani-Jelodar

Ilatikhameneh

Kim

et al. 2016

IEEE Trans. Nanotechnology

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A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as SiO2, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness (TOX) for each gate stack, including SiO2 interface layer and one high-k material. For the same EOT, Al2O3 (k=9) over 3Å SiO2 provides the best performance, while for HfO2 (k=20) and La2O3 (k=30), SiO2 thicknesses should be 5Å and 7Å, respectively. The effects of using high-k oxides and gate stacks on the performance of ultra-scaled MOSFETs are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.

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Section: Methodsmentioning

confidence: 82%

Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

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Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Salmani-Jelodar

Ilatikhameneh

Kim

et al. 2016

IEEE Trans. Nanotechnology

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“…The description of work is as follows: Section 2 describes the construction of the proposed Different dielectric MOSFET and the simulation settings and calibrates the traditional n-type MOSFET [24]. The suggested device's simulation results are produced and explained in section 3.…”

Section: Introductionmentioning

confidence: 99%

Influence of Device Performance of Sub-15 nm high K dielectric-based MOSFETs over Conventional Si-based MOSFETs.

Singh

Baghel

Tirkey

2022

Preprint

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A channel-engineered single insulator gate metal oxide field effect transistor (MOSFET) for low-power digital circuitry has been proposed in this study. This study examines the effects of several dielectric insulators used as gate materials, silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium dioxide (HfO2), and zirconium dioxide (ZrO2). The device's performance parameters are enhanced by utilizing different dielectrics in MOSFETs as a gate dielectric since the leakage current is significantly decreased. Following the validation of simulation findings using MOSFET reference data, the structure is evaluated by 15nm and 20nm node technology. In particular 15 nm scale, MOSFET exhibits reduced IOFF, higher ION/IOFF ratio, enhanced Drain Induced Barrier Lowering (DIBL), and Sub-threshold Slope (SS). For proposed MOSFETs, the simulated values of ION, IOFF, ION/IOFF, SS, DIBL, TGF, output conductance (gd), intrinsic gain (Av), and early voltage (VEA) shows improvements which are helpful in digital logic applications.

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Digital Performance Analysis of Double Gate MOSFET by Incorporating Core Insulator Architecture

Jaiswal

Gupta

2022

Silicon

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Performance degradation due to thicker physical layer of high k oxide in ultra-scaled MOSFETs and mitigation through electrostatics design

Cited by 4 publications

References 4 publications

Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Influence of Device Performance of Sub-15 nm high K dielectric-based MOSFETs over Conventional Si-based MOSFETs.

Digital Performance Analysis of Double Gate MOSFET by Incorporating Core Insulator Architecture

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