Performance and power optimization through data compression in Network-on-Chip architectures

Adaptive data compression for high-performance low-power on-chip networks

“…Table 4. Compared with the previous proposal based on runs of zero bits in a word [4], our table-based compression achieves 14% better hit rate (up to 25%). Due to a large compression gain from zeros, a special treatment such as pinning a zero value in the table would be desirable.…”

“…Figure 3 shows the structure of 4-entry tables for a 16-PE network, where the encoding table is for PE4 and the decoding table is for PE8. The encoding table shows that A, the value of the first entry, is used by six receiver PEs (0, 4,7,8,12,14). Likewise, the decoding table shows that A, the value of the second entry, is used by four sender PEs (2,4,11,15).…”

“…Our design uses a tablebased compression approach by dynamically tracking value patterns in traffic. Using a table for compression hardware processes diverse value patterns adaptively rather than taking static patterns based on zero bits in a word [4]. The tablebased approach can easily achieve a better compression rate by increasing the table size.…”

“…Bus compression also expands the bus width by encoding a wide data as a small size code [17], [18]. Recently data compression is explored in the on-chip network domain for performance and power [4].…”

“…This ever-increasing integration of components in a single chip has embarked the beginning of interconnect-centric designs [1]- [4]. At the same time, as the shrinking technology continues to exacerbate the imbalance between gate and wire in terms of delay and power, onchip interconnects are predicted to be a crucial factor in designing a CMP system [5], [6].…”