Performance analysis of InAs- and GaSb-InAs-based independent gate tunnel field effect transistor RF mixers

Pown, M.; Lakshmi, B.

doi:10.1007/s10825-017-1005-8

Cited by 4 publications

(1 citation statement)

References 19 publications

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“…Besides, the Fermi -Dirac statistics and SRH recombination, Hurkx tunneling model is also used in the simulator. The device dimensions, appropriate models for the device simulator and the DC characteristics obtained are taken from our previous calibrated results [22]. It can be noticed that low-band gap material with low effective mass (m*) can be used to improve the drive current of the device [23]- [24].…”

Section: Device Description and Parameter Spacementioning

confidence: 99%

Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic

Boggarapu

Pown

et al. 2022

International Journal of Electronics

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This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 10 3 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 10 3 times and less propagation delay than that of hetero-junction NOR logic circuit.The structure of TFET consists of a p-i-n junction (ptype, intrinsic, n-type), in which the tunneling of electrons B. Lokesh

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Section: Device Description and Parameter Spacementioning

confidence: 99%