Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

Abstract

. Performance analysis and optimization of high density tree-based 3d multilevel FPGA. Abstract. A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multilevel network with the logic blocks placed at different Tree levels using ButterflyFat-Tree network topology. 2D physical layout development of a Tree-based multilevel interconnect network is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to redistribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers discussed. The impact of of Through Silicon Vias and performance improvement on 3D Tree-based FPGA analyzed and also an optimized physical design technology leveraging on TSV, Thermal-TSV (TTSV), and thermal analysis are presented. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and a performance improvement of 53% recorded in our place and route experiments.

Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology

“…The experiments carried out in our laboratory and recent publications points out that the utilization of TSVs is actually very low in 3D Mesh-based FPGAs with full vertical connectivity [25], which motivates us to explore new architectures that can be better optimized to achieve higher speed, logic density, reduced power consumption and area to minimize the gap between FPGAs and ASICs. In this paper, we prefer to use a Tree-based multilevel FPGA architecture, because from our experimental and design experience, we believe, due to the BFT based multilevel interconnect topology, Tree-based FPGA architectures is more suitable to build high density 3D re-configurable systems compared to Mesh-based industrial FPGAs [8]. In a Tree-based FPGA architecture [8], [10], the programmable interconnects are arranged in a BFT based multilevel network with the switch blocks placed at different tree levels and the logic blocks (LBs) are grouped into clusters.…”

“…In this paper, we prefer to use a Tree-based multilevel FPGA architecture, because from our experimental and design experience, we believe, due to the BFT based multilevel interconnect topology, Tree-based FPGA architectures is more suitable to build high density 3D re-configurable systems compared to Mesh-based industrial FPGAs [8]. In a Tree-based FPGA architecture [8], [10], the programmable interconnects are arranged in a BFT based multilevel network with the switch blocks placed at different tree levels and the logic blocks (LBs) are grouped into clusters. Due to the multilevel network arrangement, we do not have to deal with 3D SBs in the case of Tree-based FPGA, rather all the switch blocks remain as 2D and only the signal and I/O communications that are partitioned between multi-tiers are interconnected using TSVs.…”

Architecture level TSV count minimization methodology for 3D tree-based FPGA

“…In a Tree-based FPGA architecture [4], The Logic Blocks (LBs) are grouped into clusters located at different levels. Each cluster contains a switch block to connect local LBs.…”

“…As illustrated in Figure 1, the Tree-based FPGA architecture unifies two unidirectional upward and downward interconnection networks using a Butterfly Fat-Tree topology to connect Downward MSBs (DMSB) and Upward MSBs (UMSB) to LBs inputs and outputs. A 3D interconnection network architecture for Tree-based FPGA presented in [4]. As illustrated in Figure 1, in a Tree-based FPGA architecture, the programmable interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels.…”

“…The TSV count minimization methodology is developed using Rent's parameter based iterative negotiation based on 3D Tree-based FPGA router [4] program. The aim is to find the best tradeoff between device routability and interconnect requirement of each MCNC application.…”