Passivation of Amorphous Oxide Semiconductors Utilizing a Zinc–Tin–Silicon–Oxide Barrier Layer

Sundholm, Eric Steven; Presley, Rick E.; Hoshino, Ken; Knutson, Christopher C.; Hoffman, Randy; Mourey, Devin A.; Keszler, Douglas A.; Wager, John F.

doi:10.1109/led.2012.2191530

Cited by 19 publications

(20 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Details of how we fabricate and test our AOS TFTs have been discussed elsewhere . Briefly, we employ a bottom‐gate TFT architecture using a 100‐nm‐thick thermal silicon dioxide gate insulator on a silicon substrate.…”

Section: Sample Preparationmentioning

confidence: 99%

“…AOS TFT channel layers are patterned via aluminum shadow masks with W / L = 2000 µm/200 µm. Some coplanar AOS TFTs are passivated using a 100‐nm‐thick RF magnetron sputtered zinc–tin–silicon oxide (ZTSO) subjected to a 400 °C post‐deposition annealing for 1 h in air . As‐fabricated transfer curves are measured within 5 days of device fabrication.…”

Section: Sample Preparationmentioning

confidence: 99%

See 1 more Smart Citation

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

Hoshino¹,

Yeh

Wager

2013

J Soc Info Display

View full text Add to dashboard Cite

An indium–gallium–zinc oxide or a zinc–tin oxide thin‐film transistor (TFT) fabricated when the relative humidity in the laboratory is less than 50% is found to exhibit good electrical performance, with an abrupt, distortion‐free transfer curve and a turn‐on voltage close to 0 V. In contrast, when such an amorphous oxide semiconductor (AOS) TFT is fabricated at a relative humidity greater than 50%, its “as‐fabricated” electrical performance is very poor, typically characterized by a large amount of hysteresis, a strongly negative turn‐on voltage, and a kink‐like distortion in the subthreshold region of its transfer curve. However, the electrical performance of such a poor‐quality TFT is observed to improve over time, if it is simply stored in the dark at room temperature without being subjected to electrical stress. This recovery usually requires weeks (months) for an unpassivated (passivated) AOS TFT. Recovery is tentatively ascribed to the gradual removal of moisture from the AOS TFT channel layer.

show abstract

Section: Sample Preparationmentioning

confidence: 99%

Section: Sample Preparationmentioning

confidence: 99%

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

Hoshino¹,

Yeh

Wager

2013

J Soc Info Display

View full text Add to dashboard Cite

show abstract

“…Details of how we fabricate and test our IGZO TFTs have been discussed elsewhere . Briefly, we employ a bottom‐gate TFT architecture using a 100‐nm‐thick thermal silicon dioxide gate insulator on a silicon substrate.…”

Section: Methodsmentioning

confidence: 99%

“…Some coplanar IGZO TFTs are passivated using a 100‐nm‐thick RF magnetron sputtered zinc tin silicon oxide (ZTSO) subjected to a 400°C post‐deposition anneal for 1 h in air . Although all of the data presented in this publication is for IGZO TFTs, very similar trends are observed for IGZO and zinc tin oxide (ZTO) TFTs …”

Section: Methodsmentioning

confidence: 99%

Negative bias illumination stress assessment of indium gallium zinc oxide thin‐film transistors

Hoshino¹,

Wager²

2015

J Soc Info Display

View full text Add to dashboard Cite

Electrical performance stability of indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) is evaluated under negative bias illumination stress (NBIS). A bottom‐gate IGZO TFT whose top surface is passivated with zinc tin silicon oxide (ZTSO) exhibits a dramatic improvement in NBIS stability compared with that of an unpassivated, bottom‐gate IGZO TFT. Oxygen chemisorption/desorption at the channel layer top surface is proposed to explain why an unpassivated TFT exhibits significantly more NBIS than a passivated TFT.

show abstract

“…Figure reveals that ZTSO passivation of an IGZO TFT leads to a very small shift in the turn‐on voltage with very little hysteresis. Once again, a ZTSO‐passivated device has lesser NBIS instability (not shown) than an unpassivated IGZO TFT . In short, ZTSO appears promising for use as an amorphous oxide semiconductor (AOS) passivation layer.…”

Section: Introductionmentioning

confidence: 96%

A framework for assessing amorphous oxide semiconductor thin‐film transistor passivation

et al. 2012

View full text Add to dashboard Cite

Amorphous oxide semiconductor thin‐film transistors (TFTs) are moving towards commercialization for a variety of display applications. Invariably, display applications require a bottom‐gate TFT configuration in which passivation of the top channel layer surface is required. The objective of this work is to propose a conceptual model framework for assessing TFT passivation schemes, within the context of amorphous oxide semiconductor electronics. This model involves first estimating the energy of the charge neutrality levels (CNLs) for the channel and passivation layers. Then, an energy band diagram is drawn to establish the relative position of these CNLs prior to their establishment of intimate contact. A situation in which the passivation layer CNL is below that of the channel layer CNL is considered undesirable because interface state electronic transfer from the channel to the passivation layer leads to formation of an accumulation layer at this interface. Although the opposite case in which the passivation layer CNL is above that of the channel layer CNL is more desirable, the ideal situation would be when both CNLs align because no interface state electronic transfer would occur. This framework is then employed in a discussion of the passivation of indium gallium zinc oxide and zinc tin oxide bottom‐gate TFTs.

show abstract

Passivation of Amorphous Oxide Semiconductors Utilizing a Zinc–Tin–Silicon–Oxide Barrier Layer

Cited by 19 publications

References 8 publications

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

Negative bias illumination stress assessment of indium gallium zinc oxide thin‐film transistors

A framework for assessing amorphous oxide semiconductor thin‐film transistor passivation

Contact Info

Product

Resources

About