PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies

Yuan, Zihao; Shukla, Prachi; Chetoui, Sofiane; Nemtzow, Sean S.; Reda, Sherief; Coskun, Ayse K.

doi:10.1109/tcad.2021.3079166

Cited by 11 publications

(3 citation statements)

References 46 publications

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“…Widely used modelling tools such as finite element models for thermal simulation [2] are lacking in this regard as the number of required elements and hence the computational time rapidly increases for capturing details at the smallest scales [3]. In order to solve this problem, there have been many efforts in recent studies to make the simulation process more efficient [4]. Recent fast compact thermal modelling methodologies for the temperature distribution prediction in 2D and 3D chip packages include the Hotspot tool [5], [6] and the Power Blurring method [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Benchmarking of Machine Learning Methods for Multiscale Thermal Simulation of Integrated Circuits

Coenen

Oprins

Degraeve

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Multiscale thermal analysis in integrated systems is required for capturing both device-level and circuit-level dynamics. Traditional analysis with finite element (FE) models can be accelerated by using machine learning (ML) methods. In this paper a performance benchmarking between three ML methods for thermal simulation is carried out: Artificial Neural Networks (ANNs), Proper Orthogonal Decomposition with Radial Basis Functions (POD-RBF) and finally POD-RBF-ANN is used as a hybrid ML method. The (dis)advantages of the different methods are demonstrated for the thermal simulation of a multiscale photonic chip. The ML models are trained with FE data for both linear and non-linear dynamics and are tested for inter-and extrapolation prediction accuracy. A computational speed increase with factor >7500 compared to FE is obtained. Furthermore, ANNs prove to be the best suited for the simulation of non-linear dynamics. POD-RBF is the best method for minimizing training time and combining the best of both methods in POD-RBF-ANN creates a ML model with short training phase and highly accurate predictions.

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Section: Introductionmentioning

confidence: 99%

Benchmarking of Machine Learning Methods for Multiscale Thermal Simulation of Integrated Circuits

Coenen

Oprins

Degraeve

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…

is the node temperature matrix that can be solved from Equation 1 . This thermal RC equation matrix can be solved using differential solvers, such as LU decomposition solvers, to obtain the steady-state temperature of each thermal node ( Skadron et al., 2003 ; Yuan et al, 2021 ). Solving this first-order RC matrix is apparently faster than solving the second-order heat equations ( Pedram and Nazarian, 2006 ).…”

Section: Introductionmentioning

confidence: 99%

Neural network-based cooling design for high-performance processors

Yuan

Coskun

2022

iScience

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Summary Ultra-high chip power densities that are expected to surpass 1-2kW/cm 2 in future high-performance systems cannot be easily handled by conventional cooling methods. Various emerging cooling methods, such as liquid cooling via microchannels, thermoelectric coolers (TECs), two-phase vapor chambers, and hybrid cooling options have been designed to efficiently remove heat from high-performance processors. However, selecting the optimal cooling solution for a given chip and determining the optimal cooling parameters for that solution to achieve high efficiency are open problems. These problems are, in fact, computationally expensive because of the massive space of possible solutions. To address this design challenge, this article introduces a deep learning-based cooling design optimization flow that rapidly and accurately converges to the optimal cooling solution as well as the optimal cooling parameters for a given chip floorplan and its power profile.

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“…In Figure 1, when the chip is working, the temperature distribution on the chip is not uniform, especially for some large array and high-power chips, the overall temperature distribution has the characteristics of large drop and multi-center [2], and different operating temperatures also have an impact on the chip performance, which puts forward the demand for the on-chip temperature measurement function. Most of the existing image sensor solutions with temperature sensors use traditional integrated temperature sensors to be placed in the corners or surroundings of the image sensor chip, which is difficult to cover the entire chip, the temperature measurement effect is very limited, and it is difficult to achieve comprehensive and accurate image correction for each or part of the pixels.…”

mentioning

confidence: 99%

Pixel-level temperature sensor design for image sensors

Zhang

Chen

Yao

et al. 2023

Conference on Infrared, Millimeter, Terahertz Waves and Applications (IMT2022)

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With the development of science and technology, image sensors are more and more widely used, such as digital cameras and surveillance cameras. However, due to the physical characteristics of the photodetector, which performance is sensitive to the variation of the operating temperature. Therefore, a digital temperature sensor integrated on the chip is required to measure the operating temperature and assist in correction and compensation. Traditional scheme integrates one temperature sensor on the whole image sensor chip, which can't reflect the temperature distribution for each pixel.It's desirable to implement temperature measurement in pixel level for accurate correction, but existing temperature sensor occupying area of hundred μm 2 , which can't be input to the pixel of image sensor. In additional, the power consumption of each temperature sensor isμW-level, which will dissipate considerable power for million temperature sensors. In this paper, a pixel-level integrated temperature sensor is proposed. The circuit is composed of only a capacitor and a conventional diode. The readout circuit is similar to that of the active pixel of image sensor, thus the ADC (Analog-to-Digital Converter) and other readout circuits and be multiplexed. The temperature sensor integrated in pixel is designed, which area is only 0.21 μm 2 . The simulation results show the increased power consumption for 50Hz working pixels don't exceed 4%. It's confirmed that the proposed pixel-level integrated temperature sensor can measure the temperature of each pixel and assisting in the accurate correction of image sensor in pixel level.

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PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies

Cited by 11 publications

References 46 publications

Benchmarking of Machine Learning Methods for Multiscale Thermal Simulation of Integrated Circuits

Benchmarking of Machine Learning Methods for Multiscale Thermal Simulation of Integrated Circuits

Neural network-based cooling design for high-performance processors

Pixel-level temperature sensor design for image sensors

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