Packet-level static timing analysis for NoCs

Krimer, Evgeni; Erez, Mattan; Keslassy, Isaac; Kolodny, Avinoam; Walter, Isask'har

doi:10.1109/nocs.2009.5071451

Cited by 4 publications

(3 citation statements)

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“…In order to maintain high throughput and low latency, reducing network congestion with migrating some workload fro m busy links to idle lin ks is an effective solution. In [11], Krimer makes a packet-level static timing analysis to advise optimization decision. When mu ltiple flows share a same link, and the overall bandwidth requirement is beyond link's capacity.…”

Section: IImentioning

confidence: 99%

Bandwidth-based Application-Aware Multipath Routing for NoCs

Ding¹,

Yang²,

Ren³

et al. 2015

Proceedings of the International Conference on Computer Information Systems and Industrial Applications

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Abstract--Most of routing algorithms for On-chip communication are neither application-aware nor routing packets using multiple paths. In addition, they hardly consider link bandwidth variation resulting from widely applied global asynchronous local synchronous (GALS ) mechanism. In this paper, we propose a bandwidth-based application-aware multipath routing (BAMR) algorithm to assign multiple routing paths by leveraging the knowledge of application and network bandwidth features. With the increase of number of flows resulting from the split of flows, we present a new method named dynamic-amount fixed-number (DAFN) flow control mechanism to avoid deadlock. We compare our algorithm with XY, YX, an d O1TURN with synthetic traffic patterns and traffic trace of parallel implementation of H.264. Experiments demonstrate that BAMR achieves higher throughput with decrease in latency. Furthermore, the proposed algorithm achieves better workload balance by distributing traffic over multiple paths.

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Section: IImentioning

confidence: 99%

Bandwidth-based Application-Aware Multipath Routing for NoCs

Ding¹,

Yang²,

Ren³

et al. 2015

Proceedings of the International Conference on Computer Information Systems and Industrial Applications

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“…Figure 1 illustrates the delay evaluation of a heterogeneous NoC for two existing extreme analysis methodologies: single-VC [2,5,15,16] and "infinite-VCs", i.e. assuming that virtual channels are always available for any flow [6,12,1]. Single-VC based methodologies can result in higher latencies due to the over-estimation of path acquisition latencies (i.e.…”

Section: Introductionmentioning

confidence: 99%

“…Previous works have presented analysis methodologies for NoCs with a single-VC [2,5,15,16], a uniform (same for all links) number of VCs [19,10,9,13] and "infinite" number of VCs [6,12,1].…”

Section: Introductionmentioning

confidence: 99%

Delay analysis of wormhole based heterogeneous NoC

Ben-Itzhak

Cidon

Kolodny

2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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We introduce a novel evaluation methodology to analyze the delay of a wormhole routing based NoC with variable link capacities and a variable number of virtual channels per link. This methodology can be utilized to analyze different heterogeneous NoC architectures and traffic scenarios for which no analysis framework has been developed before. In particular, it can replace computationally-extensive simulations at the inner-loop of the link capacities and virtual channels allocation steps of the NoC topology optimization process. Our analysis introduces a set of implicit equations which can be efficiently solved iteratively. We demonstrate the accuracy of our approximation by comparing the analysis results to a simulation model for several use-cases and synthetic examples. In addition, we compare the analysis with simulation results for a chip-multi-processor (CMP) using SPLASH-2 and PARSEC traces for both homogeneous and heterogeneous NoC configurations.

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