Overview and perspectives of depleted CMOS sensors for high radiation environments

Abstract

To cope with increased radiation levels expected at the HL-LHC new approaches are being investigated using monolithic CMOS pixel detectors where readout electronics and depleted charge collection layer are combined. Those devices rely on radiation hard process technology, multiple nested wells, high resistivity substrates and ability to apply high voltage bias to achieve significant depletion depths. They can be thinned and backside processed for biasing. Since 2014, members of more than 20 groups in ATLAS are collaborating in CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterization with the goal to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. Many CMOS technology vendors have been approached in this effort. This contribution introduces challenges for the usage of CMOS pixel detectors at HL-LHC and gives a summary of different concepts and the current state of designs of depleted CMOS prototypes.

Overview of CMOS Sensors for Future Tracking Detectors

“…Since a high bias voltage can be applied to the device, there will be on average shorter drift distances and, as a consequence, a higher radiation tolerance capability. However, the sensor capacitance is larger in this structure, up to hundreds of fF [4] depending on the pixel size, so the noise will be also larger. The electronics will also have lower speed and will need more power to counterbalance this fact.…”

“…Therefore, longer drift distances are required on average and consequently, this structure tends to a lower radiation tolerance. Nevertheless, the sensor capacitance is very small, a few fF [4], having a lower noise compared to the large fill-factor structure. Thus, the electronics implemented in the small fill-factor structure can be faster and less power-consuming.…”

Depleted CMOS sensors for HL-LHC

“…The total input capacitance to the amplifier, represented by the n-well capacitance to all boundaries plus the capacitance between the deep p-well and the deep n-well, is large (up to several 100 fF, depending on layout), influencing the noise, power, and timing performance [8]. In addition, potential capacitive coupling of digital transient signals into the sensor must be prevented by dedicated design.…”

Depleted Monolithic Active Pixel Sensors in the LFoundry 150 nm and TowerJazz 180 nm CMOS Technologies

“…The main limiting factor for these devices is the predominant diffusion movement for charge collection. Hence, during the last decade, there has been a trend to improve the depletion within the sensitive layer of CMOS pixels [4], leading eventually to designs with fast charge collection through drift, namely DMAPS. Recently, significant progress has been made for DMAPS devices with several large-scale demonstrator chips developed in different CMOS technologies [5][6][7][8][9].…”