Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing

Ryu, Seong-Wan; Min, Kyungkyu; Jungho, Shin; Kwon, Hyosang; Nam, Donghoon; Oh, Taekyung; Jang, Tae Ho; Yoo, Min-Soo; Kim, Yongtaik; Hong, Seongin

doi:10.1109/iedm.2017.8268437

Cited by 52 publications

(33 citation statements)

References 8 publications

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“…Although several comments above have lamented the absence of the main DRAM manufacturers in the technical RH literature, possibly the most important experimental work at the silicon level comes from this group. Ryu et al [13] from SK Hynix showed experimentally that RH susceptibility was correlated with both cell transistor threshold voltage (higher threshold giving lower susceptibility) and cell transistor charge pumping current (higher current giving higher susceptibility). The effect of the threshold voltage is consistent with RH being partially caused by capacitive coupling between the switching aggressor wordline and the adjacent victim wordlines causing subthreshold leakage to drain the charged capacitor.…”

Section: Experimental and Simulation Data At Silicon Levelmentioning

confidence: 99%

“…Experimental evidence points to two mechanisms for the RH disturb, namely cell transistor subthreshold leakage and electron injection into the p-well of the DRAM array from the hammered cell transistors and their subsequent capture by the storage node (SN) junctions [13]. Regarding the subthreshold leakage, lower cell transistor threshold voltages have been shown to correlate with higher susceptibility to RH.…”

mentioning

confidence: 99%

“…The first describes a collapsing inversion layer associated with the hammered cell transistor where a population of electrons is injected into the p-well as the transistor's gate turns off [16]. The second describes electron injection from charge traps near the silicon/gate dielectric interface of the cell select transistor [13], [17]. Several studies look into techniques for hampering the migration of these injected electrons.…”

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confidence: 99%

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On DRAM Rowhammer and the Physics of Insecurity

Walker¹,

Lee

Beery³

2021

IEEE Trans. Electron Devices

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The dynamic random access memory (DRAM) disturb known as rowhammer (RH) has come to dominate the insecurity of computing systems worldwide. Several studies have concentrated on electron injection from a switching cell select transistor and capture by nearby storage node junctions as being the main mechanism for the effect. This article for the first time looks in-depth at RH from the point of view of both electron injection and capture, and capacitive crosstalk. The absence of such comprehensive studies at the silicon level in the literature can be attributed to its sensitive nature within the industry and highlights the difficulty of DRAM scaling. This review article, therefore, forms a broad foundation to extend understanding of this dangerous disturb mechanism and in so doing provides an informed view on the ability of future DRAM technologies to solve RH once and for all. Index Terms-Crosstalk, dynamic random access memory (DRAM), electron injection, rowhammer (RH). I. INTRODUCTION T HE story of dynamic random access memory (DRAM) is that of the semiconductor industry itself [1], [2]. Fifty years of scaling a field-effect transistor and a capacitor has resulted in DRAM as the "main memory" in all compute systems from cloud servers through laptops to mobile phones. This success makes such systems prone to any security weakness that may lurk within DRAM itself. The DRAM disturb known as rowhammer (RH) has been causing increasing concern since its public unmasking in [3]. It is characterized by corrupted data in cells close to a row that is turned on and off many times between data refresh. Although the actual problem seems to have been known since 2010, and most probably before that within DRAM Research and Development, with some patent applications in 2012, RH was propelled to the forefront of hardware security issues when it was used to gain computer kernel privileges [4]. After ten years from the first inkling of a problem, the RH disturb varies widely between Manuscript

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Section: Experimental and Simulation Data At Silicon Levelmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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On DRAM Rowhammer and the Physics of Insecurity

Walker¹,

Lee

Beery³

2021

IEEE Trans. Electron Devices

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“…However, S-FinFET has higher gate-induced drain leakage (GIDL) than RCAT because the overlap region between the gate and drain regions is wider in S-FinFET. Although modified S-FinFET, called RFinFET, has emerged to reduce leakage by GIDL, RFinFET still needs to operate in sub-30 nm cell size [5,6]. Minimizing I off in DRAM applications is a critical issue to achieving long refresh time.…”

Section: Introductionmentioning

confidence: 99%

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

et al. 2018

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In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I off characteristics as gate channel length decreased.Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (I on ); off-current (I off ); subthreshold slope (SS); threshold voltage (V TH ); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size. We also showed the optimized parameters of the buried insulator using a three-dimensional (3D) device simulator in sub-30 nm cell size [9]. The device described in this paper has reliable source/drain (S/D) doping concentration with a Gaussian profile. The simulator is well tuned to predict DRAM cell transistor leakage distribution [10,11]. Device StructureThe partial isolation type S-FinFET (Pi-FinFET) is a structure with a buried insulator at a certain depth from the storage node of a conventional S-FinFET. Figure 1a shows a 3D schematic of a Pi-FinFET. Silicon film thickness, buried insulator thickness, and L in , as shown in Figure 1a,b, are defined as the distance from the contact surface of the storage node to the buried insulator, the thickness of the buried insulator in the direction perpendicular to the channel, and the distance from the side gate oxide to the buried insulator, respectively. L g , L side , L ov_xj , and L ov_side represent gate channel length, the length of the side-gate in the direction parallel to the channel, the overlapped length of the side-gate and S/D doping region shown in Figure 1a, and the side-channel width shown in Figure 1c, respectively. When L side and L ov_xj are increased, the width of the overlap region of the gate and the S/D region will also increase. The n + poly gate with a gate work function of 4.2 eV was applied. L g , L side , L ov_side and the recessed depth are 30 nm, 42 nm, 10 nm, and 100 nm, respectively. RFinFET is the modified S-FinFET with a structure in which the overlap region between the side-gate and the S/D region is removed [5]. Therefore, the Pi-FinFETs proposed in this paper can be divided into Pi-SFinFET and Pi-RFinFET depending on the presence or absence of the overlap region between the side-gate and the S/D region. Namely, in...

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“…However, S-FinFET has higher gate-induced drain leakage (GIDL) than RCAT because the overlap region between the gate and the drain region is wider in S-FinFET. Although modified S-FinFET called RFinFET has emerged to reduce leakage by GIDL, RFinFET still needs to operate in sub-30nm cell size [3,4]. Minimizing Ioff in DRAM applications is a critical issue to achieve long refresh time.…”

Section: Introductionmentioning

confidence: 99%

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Lee¹,

kim²,

park³

et al. 2018

Preprint

View full text Add to dashboard Cite

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.

show abstract

Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing

Cited by 52 publications

References 8 publications

On DRAM Rowhammer and the Physics of Insecurity

On DRAM Rowhammer and the Physics of Insecurity

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

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