Organization of No. 1 ESS Central Processor

Abstract

The central processor controls the operation of the No. 1 electronic switching system by executing sequences of program instructions. The logical organization of the central processor is described by the simultaneous evolution of: (1) an instruction repertoire to carry out the required telephone and system maintenance tasks efficiently, and (2) a circuit logic design to provide the necessary circuits (flip‐flop registers, accumulators, etc.) to execute the instructions at a high data processing rate. The design aims, order structure, timing, internal sequencing, and communications with the peripheral equipment of the system are described.