To significantly reduce the FPGA/ASIC resource usage in OOFDM transceivers, numerical identifications and experimental verifications are undertaken, for the first time, of an optimum map of minimum bit-resolutions of different IFFT stages against DAC resolutions. OCIS codes: (060.2330) Fiber optic communications, (060.4080) Modulation
IntroductionOptical OFDM (OOFDM) is a promising technique for practically realizing intelligent transceivers for future elastic optical networks [1]. The inherent DSP-rich OOFDM transceivers offer salient features including, for example, automatic awareness of channel spectral characteristics, adaptability to system/network imperfections, dynamically variable capacity versus reach performance and user-controlled capability of channel add/drop multiplexing. Over the past several years, a number of real-time OOFDM implementations of transmitters [2-5], receivers [6-8] and transceivers [9,10] have been reported using FPGAs. Technically speaking, the huge FPGA logic resource usage associated with the high OOFDM DSP complexity has become one of the most significant obstacles to experimentally demonstrating real-time OOFDM transceivers having more advanced functionalities and flexibilities. For example, just the IFFT DSP algorithm alone can take >82% of the total FPGA logic resources [4]. As such several FPGAs have to be combined together to perform all necessary OOFDM DSP algorithms [6,7].From the practical application point of view, it is vital to explore effective approaches capable of minimizing, via optimizing the DSP operations, the FPGA resource usage without degrading the transceiver performance. Given the fact that the IFFT is the fundamental algorithm at the heart of the OOFDM transceivers, in this paper, special attention is, therefore, focused on the IFFT operation. As the processing speed of a typical FPGA is constrained at hundreds of MHz compared with multi-GHz DACs/ADCs, a highly parallel and pipelined IFFT architecture is thus crucial, which, however, introduces significant difficulties in reusing the complex functions that are typically employed in low-speed OFDM systems. Investigations of the impacts of the IFFT bit resolution on the OOFDM transceiver performance have been reported [11][12][13], where the IFFT operation is treated as a "black-box" without taking into account bit resolution variations between different intermediate IFFT stages.In this paper, extensive numerical explorations are undertaken, for the first time, of the IFFT stage-dependent minimum bit resolutions required for achieving the specific transceiver performance. An optimum map of minimum bit resolutions of different IFFT stages against DAC resolutions is obtained for different signal modulation formats. The high accuracy of the map is experimentally verified in a real-time FPGA platform. The map can be used to significantly reduce the FPGA logic resource usage without degrading the transceiver performance.