2016
DOI: 10.1117/12.2219358
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Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond

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Cited by 3 publications
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“…27 To reach smaller critical dimensions of <10 nm and a tighter pitch of <40 nm, the logic and memory device manufacturing industry uses self-aligned double and quadruple patterning. 28,29 Extreme ultraviolet lithography is expected to be used for the upcoming 7 nm technology node and in further technology nodes. 30 In this work, we do not intend to prove the most extreme possibilities of ALE-assisted NIL stamp fabrication and pattern transfer.…”
mentioning
confidence: 99%
“…27 To reach smaller critical dimensions of <10 nm and a tighter pitch of <40 nm, the logic and memory device manufacturing industry uses self-aligned double and quadruple patterning. 28,29 Extreme ultraviolet lithography is expected to be used for the upcoming 7 nm technology node and in further technology nodes. 30 In this work, we do not intend to prove the most extreme possibilities of ALE-assisted NIL stamp fabrication and pattern transfer.…”
mentioning
confidence: 99%