On thermal effects in deep sub-micron VLSI interconnects

Abstract

This paper presents a comprehensive analysis of the thermal effh in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upperlevel signal lines are investigated.

Thermal-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems

“…Having a uniform temperature distribution has several advantages: lowers the probability of failure [10], contributes against the exponential increase of both static and dynamic power dissipation [11] and can lead to higher performance as well [12]. Several solutions have been proposed, but none of them was able to consider the floorplanning problem at a high level of abstraction: most of the works like [13] take in consideration sub-circuit partitioning or routing tracks [14]; others [15], [16] are more focused on power models.…”

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

“…For a given cell (a, b), its power density is denoted by f ab , and its average inhomogeneous temperature is denoted by T i ab . According to (8), when there are multiple layers of heat sources, the inhomogeneous solution T i at a given target layer, e.g., layer q, can be obtained by superposing each inhomogeneous solution at layer q caused by a single layer of heat sources. Therefore, it is adequate by providing an algorithm that evaluates the inhomogeneous solution T i at layer q, caused by the heat sources at only one layer, e.g., layer p. Layer q is illustrated in Fig.…”

“…5(b). Insert eigen-expansion (11) into (8) and carry out that integral by convoluting the multilayer heat-conduction Green's function with the power density distribution at layer p. Then, the inhomogeneous temperature at an arbitrary location (x, y, z), T i (x, y, z), is derived as follows:…”

“…The inhomogeneous solution T i has been given in the form of (8). To solve the required heat-conduction Green's function G from its governing equations in (7), this paper employs the eigen-expansion technique [38].…”

“…Notably, the chip temperature gradients in lieu of a set of worst or best case chip temperature values must be considered to control the clock skews and to avoid synchronization failures under widely varying operating conditions of a chip [7]. On the other hand, the increased power density and the resulting elevation of temperature inside a chip will reduce the mean time to fail of metal wires due to accelerated electromigration of metal ions as described by the well-known Black's equation [8], [9]. To meet the stringent requirements of IC reliability concurrently with high performance of the IC, thermal-aware chip design has now become a part and parcel of chip design flow that incorporates repetitive full-chip thermal analysis over millions of transistors and interconnects [10].…”