On the structural and electrical properties of metal–ferroelectric–high k dielectric–silicon structure for non-volatile memory applications

Abstract

In this article, we report the structural and electrical properties of metal-ferroelectric-high k dielectric-silicon (MFeIS) gate stack for non-volatile memory applications. Thin film of sputtered SrBi 2 Nb 2 O 9 (SBN) was used as ferroelectric material on 5-15 nm thick high-k dielectric (Al 2 O 3 ) buffer layer deposited using plasma-enhanced atomic layer deposition (PEALD). The effect of annealing on structural and electrical properties of SBN and Al 2 O 3 films was investigated in the temperature range of 350-1000 • C. X-ray diffraction results of the SBN and Al 2 O 3 show multiple phase changes with an increase in the annealing temperature. Multiple angle ellipsometry data show the change in the refractive index (n) of SBN film from 2.0941 to 2.1804 for non-annealed to samples annealed at 600 • C. For Al 2 O 3 film, n < 1.7 in the case of PEALD and n > 1.7 for sputtered film was observed. The leakage current density in MFeIS structure was observed to two orders of magnitude lower than metal/ferroelectric/silicon (MFeS) structures. Capacitance-voltage (C-V) characteristics for the voltage sweep of −10 to 10 V in dual mode show the maximum memory window of 1.977 V in MFeS structure, 2.88 V with sputtered Al 2 O 3 and 2.957 V with PEALD Al 2 O 3 in the MFeIS structures at the annealing temperature of 500 • C.

Structural and electrical properties of Al/BiFeO3/ZrO2/n-Si structure for non-volatile memory application

“…From the graph, it has been observed that the minimum leakage current density is order of 10 −5 -10 −6 A cm −2 at − 7 V in the annealing temperature ranging from 400 to 600 °C. A minimum leakage current density has been observed at the annealing temperature of 500 °C which signifies that there is low trap density, improvement in interface at BFO/Si and deposited film properties [45]. At 500 °C, the minimum current density is observed at gate voltage of − 1 V due to direct tunnelling of charge carriers through defects present in the annealed film.…”

Gd-Doped HfO2 Memristor Device, Evaluation Robustness by Image Noise Cancellation and Edge Detection Filter for Neuromorphic Computing

“…Actually, reduced leakage current is obtained because of low trap density and better electron mobility for 600 • C device compared to 800 • C annealed device. As-formed device found increment in the trap density which results in trap assisted tunneling that increases the leakage current and decreases the non-volatile performance of the device [33]. Figure 4 (b) shows the interface level traps (Dit) with respect to E-Ev curvature of as-formed and annealed devices.…”